/external/llvm/lib/Target/R600/ |
R600MachineScheduler.cpp | 201 if (MI->getOpcode() != AMDGPU::COPY) 257 switch (MI->getOpcode()) { 278 TII->isCubeOp(MI->getOpcode()) || 279 TII->isReductionOp(MI->getOpcode()) || 280 MI->getOpcode() == AMDGPU::GROUP_BARRIER) { 284 if (TII->isLDSInstr(MI->getOpcode())) { 322 int Opcode = SU->getInstr()->getOpcode(); 381 int DstIndex = TII->getOperandIdx(MI->getOpcode(), AMDGPU::OpName::dst);
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AMDGPUMCInstLower.cpp | 34 OutMI.setOpcode(MI->getOpcode());
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R600ExpandSpecialInstrs.cpp | 71 switch (MI.getOpcode()) { 192 unsigned Opcode = BMI->getOpcode(); 212 bool IsReduction = TII->isReductionOp(MI.getOpcode()); 214 bool IsCube = TII->isCubeOp(MI.getOpcode()); 288 unsigned Opcode = MI.getOpcode();
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/external/llvm/lib/Target/SystemZ/ |
SystemZElimCompare.cpp | 118 switch (MI->getOpcode()) { 169 unsigned Opcode = MI->getOpcode(); 184 if (Branch->getOpcode() != SystemZ::BRC || 216 unsigned Opcode = TII->getLoadAndTest(MI->getOpcode()); 234 int Opcode = MI->getOpcode(); 305 switch (Compare->getOpcode()) { 369 unsigned FusedOpcode = TII->getCompareAndBranch(Compare->getOpcode(), 378 if (Branch->getOpcode() != SystemZ::BRC)
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/external/llvm/lib/CodeGen/SelectionDAG/ |
TargetLowering.cpp | 270 switch (Op.getOpcode()) { 278 if (Op.getOpcode() == ISD::XOR && 285 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0), 330 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT, 379 if (Op.getOpcode() != ISD::UNDEF) 387 switch (Op.getOpcode()) { 531 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0), 593 if (InOp.getOpcode() == ISD::SRL && 618 if (InOp.getNode()->getOpcode() == ISD::ANY_EXTEND) { 657 if (InOp.getOpcode() == ISD::SHL & [all...] |
/external/llvm/lib/Target/ARM/ |
ARMISelDAGToDAG.cpp | 291 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) { 308 return N->getOpcode() == Opc && 343 if (N->getOpcode() != ISD::ADD) 433 if (Use->getOpcode() == ISD::CopyToReg) 442 unsigned Opcode = MCID.getOpcode(); 483 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode()); 507 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode()); 533 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB && 535 if (N.getOpcode() == ISD::FrameIndex) [all...] |
ARMBaseInstrInfo.cpp | 144 unsigned MemOpc = getUnindexedOpcode(MI->getOpcode()); 299 if (isIndirectBranchOpcode(I->getOpcode()) || 300 isJumpTableBranchOpcode(I->getOpcode())) { 304 } else if (isUncondBranchOpcode(I->getOpcode())) { 306 } else if (isCondBranchOpcode(I->getOpcode())) { 327 (isUncondBranchOpcode(I->getOpcode()) || 328 isIndirectBranchOpcode(I->getOpcode()) || 329 isJumpTableBranchOpcode(I->getOpcode()) || 371 if (!isUncondBranchOpcode(I->getOpcode()) && 372 !isCondBranchOpcode(I->getOpcode())) [all...] |
/dalvik/dexgen/src/com/android/dexgen/dex/code/ |
CstInsn.java | 88 new CstInsn(getOpcode(), getPosition(), registers, constant);
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Dop.java | 85 public int getOpcode() {
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/dalvik/dexgen/src/com/android/dexgen/rop/code/ |
DexTranslationAdvice.java | 70 switch (opcode.getOpcode()) {
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/dalvik/dx/src/com/android/dx/dex/code/ |
CstInsn.java | 88 new CstInsn(getOpcode(), getPosition(), registers, constant);
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Dop.java | 96 public int getOpcode() {
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InsnFormat.java | 56 String op = insn.getOpcode().getName(); 488 int opcode = insn.getOpcode().getOpcode(); 507 int opcode = insn.getOpcode().getOpcode();
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/external/clang/lib/StaticAnalyzer/Checkers/ |
PointerSubChecker.cpp | 39 if (B->getOpcode() != BO_Sub)
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/external/dexmaker/src/dx/java/com/android/dx/dex/code/ |
CstInsn.java | 88 new CstInsn(getOpcode(), getPosition(), registers, constant);
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Dop.java | 96 public int getOpcode() {
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InsnFormat.java | 57 String op = insn.getOpcode().getName(); 489 int opcode = insn.getOpcode().getOpcode(); 508 int opcode = insn.getOpcode().getOpcode();
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/external/llvm/lib/Target/AArch64/ |
AArch64InstrInfo.cpp | 135 switch(I->getOpcode()) { 143 Cond.push_back(MachineOperand::CreateImm(I->getOpcode())); 152 Cond.push_back(MachineOperand::CreateImm(I->getOpcode())); 185 unsigned LastOpc = LastInst->getOpcode(); 200 unsigned SecondLastOpc = SecondLastInst->getOpcode(); 208 LastOpc = LastInst->getOpcode(); 215 SecondLastOpc = SecondLastInst->getOpcode(); 326 if (I->getOpcode() != AArch64::Bimm && !isCondBranch(I->getOpcode())) 336 if (!isCondBranch(I->getOpcode())) [all...] |
/external/llvm/lib/Target/Hexagon/ |
HexagonVLIWPacketizer.cpp | 268 return ((MI->getOpcode() == Hexagon::CALLR) || 269 (MI->getOpcode() == Hexagon::CALLRv3)); 370 return (MI->getOpcode() == Hexagon::JMP); 374 switch (MI->getOpcode()) { 386 return (MI->getOpcode() == Hexagon::LOOP0_i || 387 MI->getOpcode() == Hexagon::LOOP0_r); 450 int NewOpcode = QII->GetDotOldOp(MI->getOpcode()); 567 PacketSU->getInstr()->getOpcode() == Hexagon::ALLOCFRAME || 568 PacketSU->getInstr()->getOpcode() == Hexagon::DEALLOCFRAME) [all...] |
/external/llvm/lib/Target/Mips/ |
MipsInstrInfo.cpp | 161 if (!getAnalyzableBrOpc(I->getOpcode())) 200 unsigned LastOpc = LastInst->getOpcode(); 213 SecondLastOpc = getAnalyzableBrOpc(SecondLastInst->getOpcode()); 266 switch (MI->getOpcode()) {
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/external/llvm/lib/Target/XCore/ |
XCoreRegisterInfo.cpp | 154 bool isKill = MI.getOpcode() == XCore::STWFI && MI.getOperand(0).isKill(); 170 switch (MI.getOpcode()) { 191 switch (MI.getOpcode()) { 218 switch (MI.getOpcode()) {
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/external/llvm/include/llvm/IR/ |
Instructions.h | 117 return (I->getOpcode() == Instruction::Alloca); 237 return I->getOpcode() == Instruction::Load; 359 return I->getOpcode() == Instruction::Store; 430 return I->getOpcode() == Instruction::Fence; 530 return I->getOpcode() == Instruction::AtomicCmpXchg; 674 return I->getOpcode() == Instruction::AtomicRMW; 866 return (I->getOpcode() == Instruction::GetElementPtr); [all...] |
/external/llvm/lib/CodeGen/ |
StackColoring.cpp | 259 if (BI->getOpcode() != TargetOpcode::LIFETIME_START && 260 BI->getOpcode() != TargetOpcode::LIFETIME_END) 265 bool IsStart = BI->getOpcode() == TargetOpcode::LIFETIME_START; 411 assert((MI->getOpcode() == TargetOpcode::LIFETIME_START || 412 MI->getOpcode() == TargetOpcode::LIFETIME_END) && 415 bool IsStart = MI->getOpcode() == TargetOpcode::LIFETIME_START; 515 if (I->getOpcode() == TargetOpcode::LIFETIME_START || 516 I->getOpcode() == TargetOpcode::LIFETIME_END) 604 if (I->getOpcode() == TargetOpcode::LIFETIME_START || 605 I->getOpcode() == TargetOpcode::LIFETIME_END || I->isDebugValue() [all...] |
/external/llvm/lib/Transforms/Scalar/ |
EarlyCSE.cpp | 106 return hash_combine(BinOp->getOpcode(), Overflow, LHS, RHS); 109 return hash_combine(BinOp->getOpcode(), LHS, RHS); 120 return hash_combine(Inst->getOpcode(), Pred, LHS, RHS); 124 return hash_combine(CI->getOpcode(), CI->getType(), CI->getOperand(0)); 127 return hash_combine(EVI->getOpcode(), EVI->getOperand(0), 131 return hash_combine(IVI->getOpcode(), IVI->getOperand(0), 141 return hash_combine(Inst->getOpcode(), 152 if (LHSI->getOpcode() != RHSI->getOpcode()) return false; 250 return (Res << 1) ^ Inst->getOpcode(); [all...] |
/external/clang/lib/StaticAnalyzer/Core/ |
SimpleConstraintManager.cpp | 32 switch (SIE->getOpcode()) { 53 if (BinaryOperator::isComparisonOp(SSE->getOpcode())) { 174 BinaryOperator::Opcode op = SE->getOpcode(); 190 BinaryOperator::Opcode Op = SSE->getOpcode(); 227 BinaryOperator::Opcode Op = SE->getOpcode();
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