| /libcore/support/src/test/java/libcore/java/security/ |
| StandardNames.java | 595 private static final void addRi(String cipherSuite) {
604 addRi(cipherSuite);
629 addRi( "TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256");
630 addRi( "TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256");
631 addRi( "TLS_RSA_WITH_AES_128_CBC_SHA256");
632 addRi( "TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA256");
633 addRi( "TLS_ECDH_RSA_WITH_AES_128_CBC_SHA256");
634 addRi( "TLS_DHE_RSA_WITH_AES_128_CBC_SHA256");
635 addRi( "TLS_DHE_DSS_WITH_AES_128_CBC_SHA256");
663 addRi( "TLS_DH_anon_WITH_AES_128_CBC_SHA256")
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcFrameLowering.cpp | 54 SAVEri = SP::ADDri;
87 BuildMI(MBB, I, DL, TII.get(SP::ADDri), SP::O6).addReg(SP::O6)
117 BuildMI(MBB, MBBI, dl, TII.get(SP::ADDri), SP::O6)
|
| SparcInstrInfo.td | [all...] |
| DelaySlotFiller.cpp | 484 case SP::ADDri: return combineRestoreADD(MBBI, PrevInst, TII); break;
|
| SparcInstr64Bit.td | 171 def : Pat<(add i64:$a, (i64 simm13:$b)), (ADDri $a, (as_i32imm $b))>;
|
| /external/llvm/test/CodeGen/ARM/ |
| crash-O0.ll | 17 ; This function uses the scavenger for an ADDri instruction.
|
| /external/llvm/lib/CodeGen/ |
| README.txt | 35 %reg1037 = ADDri %reg1039, 1
43 Note ADDri is not a two-address instruction. However, its result %reg1037 is an
45 PHI node. We should treat it as a two-address code and make sure the ADDri is
|
| /external/llvm/lib/Target/ARM/ |
| ARMFrameLowering.cpp | 223 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : ARM::t2ADDri;
[all...] |
| ARMAsmPrinter.cpp | [all...] |
| ARMBaseInstrInfo.cpp | 173 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
196 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
[all...] |
| ARMBaseRegisterInfo.cpp | 566 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri :
|
| ARMLoadStoreOptimizer.cpp | 327 int BaseOpc = !isThumb2 ? ARM::ADDri : ARM::t2ADDri;
573 case ARM::ADDri:
[all...] |
| ARMISelDAGToDAG.cpp | [all...] |
| ARMFastISel.cpp | 762 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;
[all...] |
| /external/llvm/docs/ |
| WritingAnLLVMBackend.rst | 725 LLVM target could model this with two instructions named ``ADDri`` and
[all...] |
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | [all...] |
