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  /external/llvm/test/CodeGen/Mips/
buildpairextractelementf64.ll 16 ; CHECK: mfc1
17 ; CHECK: mfc1
2008-08-04-Bitconvert.ll 12 ; CHECK: mfc1
hf16call32_body.ll 24 ; stel: mfc1 $4,$f12
44 ; stel: mfc1 $4,$f12
45 ; stel: mfc1 $5,$f13
67 ; stel: mfc1 $4,$f12
68 ; stel: mfc1 $5,$f14
90 ; stel: mfc1 $4,$f12
91 ; stel: mfc1 $6,$f14
92 ; stel: mfc1 $7,$f15
114 ; stel: mfc1 $4,$f12
115 ; stel: mfc1 $5,$f1
    [all...]
hf16call32.ll     [all...]
mips16_32_8.ll 42 ; 32: mfc1 {{.+}}
o32_cc_byval.ll 61 ; CHECK: mfc1 $6, $f[[F0]]
  /external/llvm/lib/Target/Mips/
Mips16HardFloat.cpp 182 std::string MI = ToFP? "mtc1 ": "mfc1 ";
279 IAH.Out("mfc1 $$2,$$f0");
283 IAH.Out("mfc1 $$2,$$f0");
284 IAH.Out("mfc1 $$3,$$f1");
286 IAH.Out("mfc1 $$3,$$f0");
287 IAH.Out("mfc1 $$2,$$f1");
292 IAH.Out("mfc1 $$2,$$f0");
293 IAH.Out("mfc1 $$3,$$f2");
295 IAH.Out("mfc1 $$3,$$f0");
296 IAH.Out("mfc1 $$3,$$f2")
    [all...]
MipsInstrFPU.td 337 def MFC1 : MFC1_FT<"mfc1", GPR32Opnd, FGR32RegsOpnd, IIFmoveC1, bitconvert>,
551 // This pseudo instr gets expanded into 2 mfc1 instrs after register
MipsSEInstrInfo.cpp 103 Opc = Mips::MFC1;
431 const MCInstrDesc& Mfc1Tdd = get(Mips::MFC1);
  /external/valgrind/main/none/tests/mips32/
MoveIns.c 24 // mfc1 rt, fs
110 "mfc1 %1, $" #FD"\n\t" \
129 "mfc1 %1, $" #FD"\n\t" \
198 "mfc1 %1, $f4\n\t" \
199 "mfc1 %2, $f5\n\t" \
220 "mfc1 %1, $" #FD"\n\t" \
242 "mfc1 %1, $" #FD"\n\t" \
253 printf("MFC1\n");
254 TESTINSNMOVE("mfc1 $t1, $f0", 0, f0, t1);
255 TESTINSNMOVE("mfc1 $t2, $f1", 4, f1, t2)
    [all...]
MoveIns.stdout.exp 0 MFC1
2 mfc1 $t1, $f0 :: fs 4.676074, rt 0x4095a266
3 mfc1 $t2, $f1 :: fs 272008302207532160516096.000000, rt 0x66666666
4 mfc1 $t3, $f2 :: fs -1.875000, rt 0xbff00000
5 mfc1 $t4, $f3 :: fs 0.000000, rt 0x0
6 mfc1 $t5, $f4 :: fs 1.875000, rt 0x3ff00000
7 mfc1 $t6, $f5 :: fs 0.000000, rt 0x0
8 mfc1 $t7, $f6 :: fs 0.000000, rt 0x252a2e2b
9 mfc1 $v0, $f7 :: fs 0.000000, rt 0x262d2d2a
10 mfc1 $v1, $f8 :: fs nan, rt 0xfffffff
    [all...]
MoveIns.stdout.exp-BE 0 MFC1
2 mfc1 $t1, $f0 :: fs 4.676074, rt 0x4095a266
3 mfc1 $t2, $f1 :: fs 272008302207532160516096.000000, rt 0x66666666
4 mfc1 $t3, $f2 :: fs -1.875000, rt 0xbff00000
5 mfc1 $t4, $f3 :: fs 0.000000, rt 0x0
6 mfc1 $t5, $f4 :: fs 1.875000, rt 0x3ff00000
7 mfc1 $t6, $f5 :: fs 0.000000, rt 0x0
8 mfc1 $t7, $f6 :: fs 0.000000, rt 0x252a2e2b
9 mfc1 $v0, $f7 :: fs 0.000000, rt 0x262d2d2a
10 mfc1 $v1, $f8 :: fs nan, rt 0xfffffff
    [all...]
vfp.c 57 "mfc1 %1, $" #RT "\n\t" \
58 "mfc1 %2, $f1\n\t" \
77 "mfc1 %1, $" #RT "\n\t" \
94 "mfc1 %0, $" #fd "\n\t" \
114 "mfc1 %1, $" #fd "\n\t" \
115 "mfc1 %2, $f1\n\t" \
round.c 94 "mfc1 %0, $f0\n\t" \
102 "mfc1 %0, $f0\n\t" \
  /frameworks/native/opengl/libagl/arch-mips/
fixed_asm.S 32 mfc1 $a0,$f12
  /external/chromium_org/v8/test/cctest/
test-assembler-mips.cc 366 __ mfc1(t0, f4);
367 __ mfc1(t1, f5);
368 __ mfc1(t2, f6);
369 __ mfc1(t3, f7);
428 __ mfc1(t2, f8);
433 __ mfc1(t3, f10);
783 __ mfc1(t0, f0);
784 __ mfc1(t1, f1);
790 __ mfc1(t0, f0); // f0 has LS 32 bits of long.
791 __ mfc1(t1, f1); // f1 has MS 32 bits of long
    [all...]
  /external/v8/test/cctest/
test-assembler-mips.cc 367 __ mfc1(t0, f4);
368 __ mfc1(t1, f5);
369 __ mfc1(t2, f6);
370 __ mfc1(t3, f7);
432 __ mfc1(t2, f8);
437 __ mfc1(t3, f10);
789 __ mfc1(t0, f0);
790 __ mfc1(t1, f1);
796 __ mfc1(t0, f0); // f0 has LS 32 bits of long.
797 __ mfc1(t1, f1); // f1 has MS 32 bits of long
    [all...]
  /dalvik/vm/arch/mips/
CallO32.S 246 mfc1 $t0,$f0 /* Get float ($f0) or double ($f1$f0) result */
247 mfc1 $t1,$f1
  /external/llvm/test/MC/Mips/
mips-fpu-instructions.s 143 # CHECK: mfc1 $6, $f7 # encoding: [0x00,0x38,0x06,0x44]
170 mfc1 $a2,$f7
  /external/chromium_org/v8/src/mips/
macro-assembler-mips.cc 975 mfc1(t8, fs);
1028 mfc1(t8, FPURegister::from_code(fs.code() + 1));
1039 mfc1(t8, FPURegister::from_code(fs.code() + 1));
1050 mfc1(t8, FPURegister::from_code(fs.code() + 1));
1061 mfc1(t8, FPURegister::from_code(fs.code() + 1));
1089 mfc1(rs, scratch);
1097 mfc1(rs, scratch);
    [all...]
macro-assembler-mips.h 234 mfc1(dst_low, src);
235 mfc1(dst_high, FPURegister::from_code(src.code() + 1));
239 mfc1(dst_high, FPURegister::from_code(src.code() + 1));
243 mfc1(dst_low, src);
    [all...]
  /art/compiler/utils/mips/
assembler_mips.h 286 void Mfc1(Register rt, FRegister fs);
  /external/llvm/test/MC/Disassembler/Mips/
mips32.txt 254 # CHECK: mfc1 $6, $f7
mips32_le.txt 254 # CHECK: mfc1 $6, $f7
mips32r2.txt 263 # CHECK: mfc1 $6, $f7

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