| /art/compiler/dex/quick/x86/ |
| utility_x86.cc | 25 LIR* X86Mir2Lir::OpFpRegCopy(int r_dest, int r_src) {
28 DCHECK_EQ(X86_DOUBLEREG(r_dest), X86_DOUBLEREG(r_src));
29 if (X86_DOUBLEREG(r_dest)) {
32 if (X86_SINGLEREG(r_dest)) {
44 LIR* res = RawLIR(current_dalvik_offset_, opcode, r_dest, r_src);
45 if (r_dest == r_src) {
73 * 1) r_dest is freshly returned from AllocTemp or
76 LIR* X86Mir2Lir::LoadConstantNoClobber(int r_dest, int value) {
77 int r_dest_save = r_dest;
78 if (X86_FPREG(r_dest)) {
[all...] |
| codegen_x86.h | 33 LIR* LoadBaseDisp(int rBase, int displacement, int r_dest, OpSize size, int s_reg);
36 LIR* LoadBaseIndexed(int rBase, int r_index, int r_dest, int scale, OpSize size);
38 int r_dest, int r_dest_hi, OpSize size, int s_reg);
39 LIR* LoadConstantNoClobber(int r_dest, int value);
144 LIR* OpFpRegCopy(int r_dest, int r_src);
149 LIR* OpRegCopy(int r_dest, int r_src);
150 LIR* OpRegCopyNoInsert(int r_dest, int r_src);
152 LIR* OpRegMem(OpKind op, int r_dest, int rBase, int offset);
154 LIR* OpRegRegImm(OpKind op, int r_dest, int r_src1, int value);
155 LIR* OpRegRegReg(OpKind op, int r_dest, int r_src1, int r_src2)
[all...] |
| fp_x86.cc | 66 int r_dest = rl_result.low_reg; local
69 if (r_dest == r_src2) {
71 OpRegCopy(r_src2, r_dest);
73 OpRegCopy(r_dest, r_src1);
74 NewLIR2(op, r_dest, r_src2);
121 int r_dest = S2d(rl_result.low_reg, rl_result.high_reg); local
124 if (r_dest == r_src2) {
126 OpRegCopy(r_src2, r_dest);
128 OpRegCopy(r_dest, r_src1);
129 NewLIR2(op, r_dest, r_src2)
[all...] |
| int_x86.cc | 112 LIR* X86Mir2Lir::OpRegCopyNoInsert(int r_dest, int r_src) {
113 if (X86_FPREG(r_dest) || X86_FPREG(r_src))
114 return OpFpRegCopy(r_dest, r_src);
116 r_dest, r_src);
117 if (r_dest == r_src) {
123 LIR* X86Mir2Lir::OpRegCopy(int r_dest, int r_src) {
124 LIR *res = OpRegCopyNoInsert(r_dest, r_src);
406 void X86Mir2Lir::OpRegThreadMem(OpKind op, int r_dest, ThreadOffset thread_offset) {
415 NewLIR2(opcode, r_dest, thread_offset.Int32Value());
|
| /art/compiler/dex/quick/mips/ |
| utility_mips.cc | 24 LIR* MipsMir2Lir::OpFpRegCopy(int r_dest, int r_src) {
27 DCHECK_EQ(MIPS_DOUBLEREG(r_dest), MIPS_DOUBLEREG(r_src));
28 if (MIPS_DOUBLEREG(r_dest)) {
31 if (MIPS_SINGLEREG(r_dest)) {
37 r_src = r_dest;
38 r_dest = t_opnd;
46 LIR* res = RawLIR(current_dalvik_offset_, opcode, r_src, r_dest);
47 if (!(cu_->disable_opt & (1 << kSafeOptimizations)) && r_dest == r_src) {
75 * 1) r_dest is freshly returned from AllocTemp or
78 LIR* MipsMir2Lir::LoadConstantNoClobber(int r_dest, int value)
[all...] |
| codegen_mips.h | 33 LIR* LoadBaseDisp(int rBase, int displacement, int r_dest, OpSize size, int s_reg);
36 LIR* LoadBaseIndexed(int rBase, int r_index, int r_dest, int scale, OpSize size);
38 int r_dest, int r_dest_hi, OpSize size, int s_reg);
39 LIR* LoadConstantNoClobber(int r_dest, int value);
144 LIR* OpFpRegCopy(int r_dest, int r_src);
149 LIR* OpRegCopy(int r_dest, int r_src);
150 LIR* OpRegCopyNoInsert(int r_dest, int r_src);
152 LIR* OpRegMem(OpKind op, int r_dest, int rBase, int offset);
154 LIR* OpRegRegImm(OpKind op, int r_dest, int r_src1, int value);
155 LIR* OpRegRegReg(OpKind op, int r_dest, int r_src1, int r_src2)
[all...] |
| int_mips.cc | 164 LIR* MipsMir2Lir::OpRegCopyNoInsert(int r_dest, int r_src) {
165 if (MIPS_FPREG(r_dest) || MIPS_FPREG(r_src))
166 return OpFpRegCopy(r_dest, r_src);
168 r_dest, r_src);
169 if (!(cu_->disable_opt & (1 << kSafeOptimizations)) && r_dest == r_src) {
175 LIR* MipsMir2Lir::OpRegCopy(int r_dest, int r_src) {
176 LIR *res = OpRegCopyNoInsert(r_dest, r_src);
|
| /art/compiler/dex/quick/arm/ |
| utility_arm.cc | 71 LIR* ArmMir2Lir::LoadFPConstantValue(int r_dest, int value) {
72 DCHECK(ARM_SINGLEREG(r_dest));
77 NewLIR2(kThumb2Vmovs_IMM8, r_dest, 0);
79 return NewLIR3(kThumb2Vsubs, r_dest, r_dest, r_dest);
83 return NewLIR2(kThumb2Vmovs_IMM8, r_dest, encoded_imm);
91 r_dest, r15pc, 0, 0, 0, data_target);
170 * 1) r_dest is freshly returned from AllocTemp or
173 LIR* ArmMir2Lir::LoadConstantNoClobber(int r_dest, int value)
[all...] |
| codegen_arm.h | 32 LIR* LoadBaseDisp(int rBase, int displacement, int r_dest, OpSize size, int s_reg);
35 LIR* LoadBaseIndexed(int rBase, int r_index, int r_dest, int scale, OpSize size);
37 int r_dest, int r_dest_hi, OpSize size, int s_reg);
38 LIR* LoadConstantNoClobber(int r_dest, int value);
143 LIR* OpFpRegCopy(int r_dest, int r_src);
148 LIR* OpRegCopy(int r_dest, int r_src);
149 LIR* OpRegCopyNoInsert(int r_dest, int r_src);
151 LIR* OpRegMem(OpKind op, int r_dest, int rBase, int offset);
153 LIR* OpRegRegImm(OpKind op, int r_dest, int r_src1, int value);
154 LIR* OpRegRegReg(OpKind op, int r_dest, int r_src1, int r_src2)
[all...] |
| int_arm.cc | 337 LIR* ArmMir2Lir::OpRegCopyNoInsert(int r_dest, int r_src) {
340 if (ARM_FPREG(r_dest) || ARM_FPREG(r_src))
341 return OpFpRegCopy(r_dest, r_src);
342 if (ARM_LOWREG(r_dest) && ARM_LOWREG(r_src))
344 else if (!ARM_LOWREG(r_dest) && !ARM_LOWREG(r_src))
346 else if (ARM_LOWREG(r_dest))
350 res = RawLIR(current_dalvik_offset_, opcode, r_dest, r_src);
351 if (!(cu_->disable_opt & (1 << kSafeOptimizations)) && r_dest == r_src) {
357 LIR* ArmMir2Lir::OpRegCopy(int r_dest, int r_src) {
358 LIR* res = OpRegCopyNoInsert(r_dest, r_src)
[all...] |
| /art/compiler/dex/quick/ |
| gen_loadstore.cc | 30 LIR* Mir2Lir::LoadConstant(int r_dest, int value) {
31 if (IsTemp(r_dest)) {
32 Clobber(r_dest);
33 MarkInUse(r_dest);
35 return LoadConstantNoClobber(r_dest, value);
78 LIR* Mir2Lir::LoadWordDisp(int rBase, int displacement, int r_dest) {
79 return LoadBaseDisp(rBase, displacement, r_dest, kWord,
92 void Mir2Lir::LoadValueDirect(RegLocation rl_src, int r_dest) {
95 OpRegCopy(r_dest, rl_src.low_reg);
97 LoadConstantNoClobber(r_dest, mir_graph_->ConstantValue(rl_src))
101 LoadWordDisp(TargetReg(kSp), SRegOffset(rl_src.s_reg_low), r_dest); local
[all...] |
| mir_to_lir.h | 506 LIR* LoadConstant(int r_dest, int value);
507 LIR* LoadWordDisp(int rBase, int displacement, int r_dest);
510 void LoadValueDirect(RegLocation rl_src, int r_dest);
511 void LoadValueDirectFixed(RegLocation rl_src, int r_dest);
531 virtual LIR* LoadBaseDisp(int rBase, int displacement, int r_dest, OpSize size, int s_reg) = 0;
534 virtual LIR* LoadBaseIndexed(int rBase, int r_index, int r_dest, int scale, OpSize size) = 0;
536 int r_dest, int r_dest_hi, OpSize size, int s_reg) = 0;
537 virtual LIR* LoadConstantNoClobber(int r_dest, int value) = 0;
[all...] |
