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  /external/llvm/test/CodeGen/AArch64/
global-alignment.ll 3 @var32 = global [3 x i32] zeroinitializer
9 %addr = bitcast [3 x i32]* @var32 to i64*
11 ; Since @var32 is only guaranteed to be aligned to 32-bits, it's invalid to
12 ; emit an "LDR x0, [x0, #:lo12:var32] instruction to implement this load.
14 ; CHECK: adrp [[HIBITS:x[0-9]+]], var32
15 ; CHECK: add x[[ADDR:[0-9]+]], [[HIBITS]], #:lo12:var32
39 ; Since @var32 is only guaranteed to be aligned to 32-bits, it's invalid to
40 ; emit an "LDR x0, [x0, #:lo12:var32] instruction to implement this load.
dp1.ll 3 @var32 = global i32 0
8 %val0_tmp = load i32* @var32
11 store volatile i32 %val1_tmp, i32* @var32
39 %val0_tmp = load i32* @var32
45 store volatile i32 %val4_tmp, i32* @var32
51 %val0_tmp = load i32* @var32
54 store volatile i32 %val4_tmp, i32* @var32
69 %val0_tmp = load i32* @var32
72 store volatile i32 %val4_tmp, i32* @var32
87 %val0_tmp = load i32* @var32
    [all...]
code-model-large-abs.ll 5 @var32 = global i32 0
43 %val = load i32* @var32
45 ; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var32
46 ; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var32
47 ; CHECK: movk x[[ADDR_REG]], #:abs_g1_nc:var32
48 ; CHECK: movk x[[ADDR_REG]], #:abs_g0_nc:var32
logical-imm.ll 3 @var32 = global i32 0
10 store volatile i32 %val0, i32* @var32
14 store volatile i32 %val1, i32* @var32
32 store volatile i32 %val0, i32* @var32
36 store volatile i32 %val1, i32* @var32
54 store volatile i32 %val0, i32* @var32
58 store volatile i32 %val1, i32* @var32
75 store i32 %val0, i32* @var32
compare-branch.ll 3 @var32 = global i32 0
9 %val1 = load volatile i32* @var32
15 %val2 = load volatile i32* @var32
zero-reg.ll 3 @var32 = global i32 0
9 store i32 0, i32* @var32
10 ; CHECK: str wzr, [{{x[0-9]+}}, #:lo12:var32]
movw-consts.ll 74 @var32 = global i32 0
79 store i32 0, i32* @var32
86 store i32 1, i32* @var32
93 store i32 65535, i32* @var32
100 store i32 65536, i32* @var32
107 store i32 4294901760, i32* @var32
114 store i32 -1, i32* @var32
addsub-shifted.ll 3 @var32 = global i32 0
9 %rhs1 = load volatile i32* @var32
12 store volatile i32 %val1, i32* @var32
15 %rhs2 = load volatile i32* @var32
18 store volatile i32 %val2, i32* @var32
21 %rhs3 = load volatile i32* @var32
24 store volatile i32 %val3, i32* @var32
28 %rhs4 = load volatile i32* @var32
31 store volatile i32 %val4, i32* @var32
34 %lhs4a = load volatile i32* @var32
    [all...]
addsub_ext.ll 5 @var32 = global i32 0
11 %lhs32 = load i32* @var32
21 store volatile i32 %res32_zext, i32* @var32
26 store volatile i32 %res32_zext_shift, i32* @var32
44 store volatile i32 %res32_sext, i32* @var32
49 store volatile i32 %res32_sext_shift, i32* @var32
76 store volatile i32 %lhs32, i32* @var32
86 %lhs32 = load i32* @var32
96 store volatile i32 %res32_zext, i32* @var32
101 store volatile i32 %res32_zext_shift, i32* @var32
    [all...]
cond-sel.ll 3 @var32 = global i32 0
11 store i32 %val1, i32* @var32
34 store i32 %val1, i32* @var32
62 store volatile i32 %val1, i32* @var32
70 store volatile i32 %val2, i32* @var32
102 store volatile i32 %val1, i32* @var32
110 store volatile i32 %val2, i32* @var32
142 store volatile i32 %val1, i32* @var32
150 store volatile i32 %val2, i32* @var32
182 store i32 %val1, i32* @var32
    [all...]
tst-br.ll 6 @var32 = global i32 0
12 %val = load i32* @var32
bitfield.ll 4 @var32 = global i32 0
11 store volatile i32 %sxt32, i32* @var32
22 store volatile i32 %uxt32, i32* @var32
35 store volatile i32 %sxt32, i32* @var32
46 store volatile i32 %uxt32, i32* @var32
72 store volatile i32 %shift1, i32* @var32
76 store volatile i32 %shift2, i32* @var32
80 store volatile i32 %shift3, i32* @var32
104 store volatile i32 %shift9, i32* @var32
108 store volatile i32 %shift10, i32* @var32
    [all...]
fcvt-fixed.ll 3 @var32 = global i32 0
12 store volatile i32 %cvt1, i32* @var32
17 store volatile i32 %cvt2, i32* @var32
32 store volatile i32 %cvt5, i32* @var32
37 store volatile i32 %cvt6, i32* @var32
58 store volatile i32 %cvt1, i32* @var32
63 store volatile i32 %cvt2, i32* @var32
78 store volatile i32 %cvt5, i32* @var32
83 store volatile i32 %cvt6, i32* @var32
func-calls.ll 7 @var32 = global i32 0
47 store i32 %int, i32* @var32
49 ; CHECK: str w0, [{{x[0-9]+}}, #:lo12:var32]
79 i32* @var32, %myStruct* byval @varstruct,
func-argpassing.ll 6 @var32 = global i32 0
41 store i32 %val0, i32* @var32
42 ; CHECK: str [[REG32]], [{{x[0-9]+}}, #:lo12:var32]
63 store i32 %val0, i32* @var32
64 ; CHECK: str [[REG32]], [{{x[0-9]+}}, #:lo12:var32]
76 %val = load i32* @var32
78 ; CHECK: ldr w0, [{{x[0-9]+}}, #:lo12:var32]
atomic-ops.ll 5 @var32 = global i32 0
50 %old = atomicrmw add i32* @var32, i32 %offset release
52 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
53 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var32
130 %old = atomicrmw sub i32* @var32, i32 %offset acquire
132 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
133 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var32
210 %old = atomicrmw and i32* @var32, i32 %offset seq_cst
212 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
213 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var32
    [all...]
literal_pools.ll 4 @var32 = global i32 0
9 %val32 = load i32* @var32
13 store volatile i32 %val32_lit32, i32* @var32
fp128.ll 58 @var32 = global i32 0
66 store i32 %val32, i32* @var32
81 store i32 %val32, i32* @var32
94 %src32 = load i32* @var32
110 %src32 = load i32* @var32
  /external/llvm/test/MC/AArch64/
elf-globaladdress.ll 11 @var32 = global i32 0
21 %val32 = load i32* @var32
22 store volatile i32 %val32, i32* @var32
48 ; OBJ: 0x{{[0-9,A-F]+}} R_AARCH64_ADR_PREL_PG_HI21 var32
49 ; OBJ: 0x{{[0-9,A-F]+}} R_AARCH64_LDST32_ABS_LO12_NC var32
  /external/llvm/test/CodeGen/PowerPC/
float-asmprint.ll 10 @var32 = global float -0.0, align 4
27 ; CHECK: var32:
  /external/llvm/test/CodeGen/X86/
float-asmprint.ll 10 @var32 = global float -0.0, align 4
33 ; CHECK: var32:
  /external/clang/test/CodeGen/
aarch64-inline-asm.c 9 void test_generic_constraints(int var32, long var64) {
10 asm("add %0, %1, %1" : "=r"(var32) : "0"(var32));
18 asm("ldr %0, %1" : "=r"(var32) : "m"(var));
ppc64-varargs-complex.c 63 // CHECK-NEXT: %[[VAR32:[A-Za-z0-9.]+]] = add i64 %[[VAR31]], 4
65 // CHECK-NEXT: %[[VAR34:[A-Za-z0-9.]+]] = inttoptr i64 %[[VAR32]] to float*
  /sdk/emulator/opengl/host/tools/emugen/
VarType.h 39 class Var32 : public VarConverter {
41 Var32() : VarConverter(4) {}
  /external/tcpdump/
print-dccp.c 412 u_int32_t *var32; local
516 var32 = (u_int32_t *)(option + 2);
517 printf(" %u",(u_int32_t)ntohl(*var32));

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