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  /external/llvm/test/CodeGen/ARM/
vld3.ll 18 ;CHECK: vld3.8 {d16, d17, d18}, [r0:64]
19 %tmp1 = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A, i32 32)
28 ;CHECK: vld3.16
30 %tmp1 = call %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3.v4i16(i8* %tmp0, i32 1)
40 ;CHECK: vld3.16 {d16, d17, d18}, [{{r[0-9]+}}], {{r[0-9]+}}
43 %tmp1 = call %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3.v4i16(i8* %tmp0, i32 1)
54 ;CHECK: vld3.32
56 %tmp1 = call %struct.__neon_int32x2x3_t @llvm.arm.neon.vld3.v2i32(i8* %tmp0, i32 1)
65 ;CHECK: vld3.32
67 %tmp1 = call %struct.__neon_float32x2x3_t @llvm.arm.neon.vld3.v2f32(i8* %tmp0, i32 1
    [all...]
2010-05-20-NEONSpillCrash.ll 4 ; the @llvm.arm.neon.vld3.v8i8 defined three parts of a register.
8 declare %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8*, i32) nounwind readonly
13 %tmp1b = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A2, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=2]
16 %tmp1d = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A4, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=2]
19 %tmp1e = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A5, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=1]
21 %tmp1f = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A6, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=1]
23 %tmp1g = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A7, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=2]
26 %tmp1h = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A8, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=2]
2012-08-27-CopyPhysRegCrash.ll 8 declare { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8(i8*, i32) nounwind readonly
22 %7 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8(i8* null, i32 1)
25 %10 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8(i8* %9, i32 1)
27 %12 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8(i8* %6, i32 1)
31 %16 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8(i8* %15, i32 1)
vldlane.ll 221 ;CHECK: vld3.8
234 ;Check the (default) alignment value. VLD3 does not support alignment.
235 ;CHECK: vld3.16 {d{{.*}}[1], d{{.*}}[1], d{{.*}}[1]}, [{{r[0-9]+}}]
249 ;CHECK: vld3.32
263 ;CHECK: vld3.32
277 ;Check the (default) alignment value. VLD3 does not support alignment.
278 ;CHECK: vld3.16 {d{{.*}}[1], d{{.*}}[1], d{{.*}}[1]}, [{{r[0-9]+}}]
293 ;CHECK: vld3.16 {d{{.*}}[1], d{{.*}}[1], d{{.*}}[1]}, [{{r[0-9]+}}], {{r[0-9]+}}
310 ;CHECK: vld3.32
324 ;CHECK: vld3.3
    [all...]
reg_sequence.ll 77 ; CHECK: vld3.8
82 %tmp1 = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=2]
309 %tmp1d = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A4, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=1]
311 %tmp1f = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A6, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=1]
337 declare %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8*, i32) nounwind readonly
vlddup.ll 132 ;CHECK: vld3.8 {d16[], d17[], d18[]}, [r2], r1
150 ;Check the (default) alignment value. VLD3 does not support alignment.
151 ;CHECK: vld3.16 {d16[], d17[], d18[]}, [r0]
  /external/llvm/test/MC/ARM/
neont2-vld-encoding.s 35 @ CHECK: vld3.8 {d16, d17, d18}, [r0:64] @ encoding: [0x60,0xf9,0x1f,0x04]
36 vld3.8 {d16, d17, d18}, [r0:64]
37 @ CHECK: vld3.16 {d16, d17, d18}, [r0] @ encoding: [0x60,0xf9,0x4f,0x04]
38 vld3.16 {d16, d17, d18}, [r0]
39 @ CHECK: vld3.32 {d16, d17, d18}, [r0] @ encoding: [0x60,0xf9,0x8f,0x04]
40 vld3.32 {d16, d17, d18}, [r0]
41 @ CHECK: vld3.8 {d16, d18, d20}, [r0:64]! @ encoding: [0x60,0xf9,0x1d,0x05]
42 vld3.8 {d16, d18, d20}, [r0:64]!
43 @ CHECK: vld3.8 {d17, d19, d21}, [r0:64]! @ encoding: [0x60,0xf9,0x1d,0x15]
44 vld3.8 {d17, d19, d21}, [r0:64]
    [all...]
neon-vld-encoding.s 157 vld3.8 {d16, d17, d18}, [r1]
158 vld3.16 {d6, d7, d8}, [r2]
159 vld3.32 {d1, d2, d3}, [r3]
160 vld3.8 {d16, d18, d20}, [r0:64]
161 vld3.u16 {d27, d29, d31}, [r4]
162 vld3.i32 {d6, d8, d10}, [r5]
164 vld3.i8 {d12, d13, d14}, [r6], r1
165 vld3.i16 {d11, d12, d13}, [r7], r2
166 vld3.u32 {d2, d3, d4}, [r8], r3
167 vld3.8 {d4, d6, d8}, [r9], r
    [all...]
  /frameworks/rs/cpu_ref/
rsCpuIntrinsics_neon_ColorMatrix.S 183 vld3.32 {d0[0],d2[0],d4[0]}, [r1]!
185 vld3.32 {d0[1],d2[1],d4[1]}, [r1]!
187 vld3.32 {d1[0],d3[0],d5[0]}, [r1]!
189 vld3.32 {d1[1],d3[1],d5[1]}, [r1]!
  /external/llvm/test/MC/Disassembler/ARM/
neont2.txt     [all...]
neon.txt     [all...]
invalid-thumbv7.txt 302 # vld3
310 # A8.6.315 VLD3 (single 3-element structure to all lanes)
359 # VLD3 multi-element size=0b11
364 # VLD3 multi-element align=0b1x
  /external/valgrind/main/none/tests/arm/
neon64.c     [all...]
neon64.stdout.exp     [all...]
  /external/pixman/pixman/
pixman-arm-neon-asm.h 152 pixldst3 vld3, 8, %(basereg+3), %(basereg+4), %(basereg+5), mem_operand variable
154 pixldst30 vld3, 8, %(basereg+0), %(basereg+1), %(basereg+2), 4, mem_operand variable
155 pixldst30 vld3, 8, %(basereg+0), %(basereg+1), %(basereg+2), 5, mem_operand variable
156 pixldst30 vld3, 8, %(basereg+0), %(basereg+1), %(basereg+2), 6, mem_operand variable
157 pixldst30 vld3, 8, %(basereg+0), %(basereg+1), %(basereg+2), 7, mem_operand variable
159 pixldst30 vld3, 8, %(basereg+0), %(basereg+1), %(basereg+2), 2, mem_operand variable
160 pixldst30 vld3, 8, %(basereg+0), %(basereg+1), %(basereg+2), 3, mem_operand variable
162 pixldst30 vld3, 8, %(basereg+0), %(basereg+1), %(basereg+2), 1, mem_operand variable
    [all...]
  /external/clang/test/CodeGen/
vld_dup.c 44 // CHECK: {{%.*}} = call { <1 x i64>, <1 x i64>, <1 x i64> } @llvm.arm.neon.vld3.v1i64(i8* {{.*}}, i32 {{[0-9]+}})
arm_neon_intrinsics.c     [all...]
  /external/llvm/lib/Target/ARM/
ARMInstrNEON.td     [all...]
ARMScheduleSwift.td     [all...]
ARMScheduleA8.td 559 // VLD3
    [all...]
ARMISelDAGToDAG.cpp     [all...]
  /external/llvm/test/Transforms/LoopStrengthReduce/ARM/
ivchain-ARM.ll 334 %vld3 = tail call <8 x i8> @llvm.arm.neon.vld1.v8i8(i8* %add.ptr7, i32 1)
345 %vadd2 = tail call <8 x i8> @llvm.arm.neon.vhaddu.v8i8(<8 x i8> %vld2, <8 x i8> %vld3) nounwind
346 %vadd3 = tail call <8 x i8> @llvm.arm.neon.vhaddu.v8i8(<8 x i8> %vld3, <8 x i8> %vld4) nounwind
  /external/clang/include/clang/Basic/
arm_neon.td 291 def VLD3 : WInst<"vld3", "3c", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
  /external/libyuv/files/source/
row_neon.cc 605 "vld3.8 {d1, d2, d3}, [%0]! \n" // load 8 pixels of RGB24.
624 "vld3.8 {d1, d2, d3}, [%0]! \n" // load 8 pixels of RAW.
    [all...]
  /external/clang/utils/TableGen/
NeonEmitter.cpp 1107 bool MultiLoadPrefix = Prefix == "vld2" || Prefix == "vld3"
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