| /external/llvm/test/CodeGen/ARM/ |
| subreg-remat.ll | 8 ; %vreg6:ssub_0<def> = VLDRS <cp#0>, 0, pred:14, pred:%noreg; mem:LD4[ConstantPool] DPR_VFP2:%vreg6
10 ; When %vreg6 spills, the VLDRS constant pool load cannot be rematerialized
34 ; %vreg2:ssub_0<def> = VLDRS <cp#0>, 0, pred:14, pred:%noreg, %vreg2<imp-def>; mem:LD4[ConstantPool]
|
| vldlane.ll | 503 ; part of %ins67 is supposed to be loaded by a VLDRS instruction in this test.)
|
| /external/llvm/lib/Target/ARM/ |
| ARMLoadStoreOptimizer.cpp | 174 case ARM::VLDRS:
345 bool isDef = (isi32Load(Opcode) || Opcode == ARM::VLDRS ||
476 case ARM::VLDRS:
604 case ARM::VLDRS:
800 case ARM::VLDRS:
825 case ARM::VLDRS:
856 bool isAM5 = (Opcode == ARM::VLDRD || Opcode == ARM::VLDRS ||
865 bool isLd = isi32Load(Opcode) || Opcode == ARM::VLDRS || Opcode == ARM::VLDRD;
[all...] |
| ARMBaseInstrInfo.cpp | [all...] |
| ARMBaseRegisterInfo.cpp | 500 case ARM::VLDRS: case ARM::VLDRD:
|
| ARMInstrVFP.td | 100 def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5:$addr),
[all...] |
| ARMCodeEmitter.cpp | [all...] |
| ARMScheduleSwift.td | [all...] |
| ARMFastISel.cpp | 549 unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS;
[all...] |
| ARMConstantIslandPass.cpp | 770 case ARM::VLDRS:
[all...] |
| /art/compiler/utils/arm/ |
| assembler_arm.h | 318 void vldrs(SRegister sd, Address ad, Condition cond = AL);
|
| assembler_arm.cc | 694 void ArmAssembler::vldrs(SRegister sd, Address ad, Condition cond) { function in class:art::arm::ArmAssembler
[all...] |
| /dalvik/vm/compiler/codegen/arm/ |
| Assemble.cpp | [all...] |
| /dalvik/vm/compiler/codegen/mips/ |
| Assemble.cpp | [all...] |
| /art/compiler/dex/quick/arm/ |
| assemble_arm.cc | [all...] |
