Lines Matching refs:opcode
226 // MR - Memory Register - opcode [base + disp], reg
228 // AR - Array Register - opcode [base + index * scale + disp], reg
230 // TR - Thread Register - opcode fs:[disp], reg - where fs: is equal to Thread::Current()
232 // RR - Register Register - opcode reg1, reg2
234 // RM - Register Memory - opcode reg, [base + disp]
236 // RA - Register Array - opcode reg, [base + index * scale + disp]
238 // RT - Register Thread - opcode reg, fs:[disp] - where fs: is equal to Thread::Current()
240 // RI - Register Immediate - opcode reg, #immediate
242 // MI - Memory Immediate - opcode [base + disp], #immediate
244 // AI - Array Immediate - opcode [base + index * scale + disp], #immediate
246 // TI - Thread Register - opcode fs:[disp], imm - where fs: is equal to Thread::Current()
248 #define BinaryOpCode(opcode) \
249 opcode ## 8MR, opcode ## 8AR, opcode ## 8TR, \
250 opcode ## 8RR, opcode ## 8RM, opcode ## 8RA, opcode ## 8RT, \
251 opcode ## 8RI, opcode ## 8MI, opcode ## 8AI, opcode ## 8TI, \
252 opcode ## 16MR, opcode ## 16AR, opcode ## 16TR, \
253 opcode ## 16RR, opcode ## 16RM, opcode ## 16RA, opcode ## 16RT, \
254 opcode ## 16RI, opcode ## 16MI, opcode ## 16AI, opcode ## 16TI, \
255 opcode ## 16RI8, opcode ## 16MI8, opcode ## 16AI8, opcode ## 16TI8, \
256 opcode ## 32MR, opcode ## 32AR, opcode ## 32TR, \
257 opcode ## 32RR, opcode ## 32RM, opcode ## 32RA, opcode ## 32RT, \
258 opcode ## 32RI, opcode ## 32MI, opcode ## 32AI, opcode ## 32TI, \
259 opcode ## 32RI8, opcode ## 32MI8, opcode ## 32AI8, opcode ## 32TI8
282 // RC - Register CL - opcode reg, CL
284 // MC - Memory CL - opcode [base + disp], CL
286 // AC - Array CL - opcode [base + index * scale + disp], CL
288 #define BinaryShiftOpCode(opcode) \
289 opcode ## 8RI, opcode ## 8MI, opcode ## 8AI, \
290 opcode ## 8RC, opcode ## 8MC, opcode ## 8AC, \
291 opcode ## 16RI, opcode ## 16MI, opcode ## 16AI, \
292 opcode ## 16RC, opcode ## 16MC, opcode ## 16AC, \
293 opcode ## 32RI, opcode ## 32MI, opcode ## 32AI, \
294 opcode ## 32RC, opcode ## 32MC, opcode ## 32AC
304 #define UnaryOpcode(opcode, reg, mem, array) \
305 opcode ## 8 ## reg, opcode ## 8 ## mem, opcode ## 8 ## array, \
306 opcode ## 16 ## reg, opcode ## 16 ## mem, opcode ## 16 ## array, \
307 opcode ## 32 ## reg, opcode ## 32 ## mem, opcode ## 32 ## array
317 #define Binary0fOpCode(opcode) \
318 opcode ## RR, opcode ## RM, opcode ## RA
383 kNullary, // Opcode that takes no arguments.
391 kShiftRegImm, kShiftMemImm, kShiftArrayImm, // Shift opcode with immediate.
392 kShiftRegCl, kShiftMemCl, kShiftArrayCl, // Shift opcode with register CL.
401 /* Struct used to define the EncodingMap positions for each X86 opcode */
403 X86OpCode opcode; // e.g. kOpAddRI
409 uint8_t opcode; // 1 byte opcode
410 uint8_t extra_opcode1; // possible extra opcode byte
411 uint8_t extra_opcode2; // possible second extra opcode byte
412 // 3bit opcode that gets encoded in the register bits of the modrm byte, use determined by the
