Lines Matching full:wide
30 rlSrc = rlSrc.wide ? dvmCompilerUpdateLocWide(cUnit, rlSrc) :33 if (rlSrc.wide) {191 assert(rlSrc1.wide);193 assert(rlSrc2.wide);195 assert(rlDest.wide);196 assert(rlResult.wide);367 if (rlDest.wide) {383 bool wide = true;388 wide = false;392 wide = false;