Lines Matching refs:src1
1296 void Assembler::and_(Register dst, Register src1, const Operand& src2,
1298 addrmod1(cond | AND | s, src1, dst, src2);
1302 void Assembler::eor(Register dst, Register src1, const Operand& src2,
1304 addrmod1(cond | EOR | s, src1, dst, src2);
1308 void Assembler::sub(Register dst, Register src1, const Operand& src2,
1310 addrmod1(cond | SUB | s, src1, dst, src2);
1314 void Assembler::rsb(Register dst, Register src1, const Operand& src2,
1316 addrmod1(cond | RSB | s, src1, dst, src2);
1320 void Assembler::add(Register dst, Register src1, const Operand& src2,
1322 addrmod1(cond | ADD | s, src1, dst, src2);
1326 void Assembler::adc(Register dst, Register src1, const Operand& src2,
1328 addrmod1(cond | ADC | s, src1, dst, src2);
1332 void Assembler::sbc(Register dst, Register src1, const Operand& src2,
1334 addrmod1(cond | SBC | s, src1, dst, src2);
1338 void Assembler::rsc(Register dst, Register src1, const Operand& src2,
1340 addrmod1(cond | RSC | s, src1, dst, src2);
1344 void Assembler::tst(Register src1, const Operand& src2, Condition cond) {
1345 addrmod1(cond | TST | S, src1, r0, src2);
1349 void Assembler::teq(Register src1, const Operand& src2, Condition cond) {
1350 addrmod1(cond | TEQ | S, src1, r0, src2);
1354 void Assembler::cmp(Register src1, const Operand& src2, Condition cond) {
1355 addrmod1(cond | CMP | S, src1, r0, src2);
1366 void Assembler::cmn(Register src1, const Operand& src2, Condition cond) {
1367 addrmod1(cond | CMN | S, src1, r0, src2);
1371 void Assembler::orr(Register dst, Register src1, const Operand& src2,
1373 addrmod1(cond | ORR | s, src1, dst, src2);
1403 void Assembler::bic(Register dst, Register src1, const Operand& src2,
1405 addrmod1(cond | BIC | s, src1, dst, src2);
1415 void Assembler::mla(Register dst, Register src1, Register src2, Register srcA,
1417 ASSERT(!dst.is(pc) && !src1.is(pc) && !src2.is(pc) && !srcA.is(pc));
1419 src2.code()*B8 | B7 | B4 | src1.code());
1423 void Assembler::mls(Register dst, Register src1, Register src2, Register srcA,
1425 ASSERT(!dst.is(pc) && !src1.is(pc) && !src2.is(pc) && !srcA.is(pc));
1427 src2.code()*B8 | B7 | B4 | src1.code());
1431 void Assembler::sdiv(Register dst, Register src1, Register src2,
1433 ASSERT(!dst.is(pc) && !src1.is(pc) && !src2.is(pc));
1436 src2.code()*B8 | B4 | src1.code());
1440 void Assembler::mul(Register dst, Register src1, Register src2,
1442 ASSERT(!dst.is(pc) && !src1.is(pc) && !src2.is(pc));
1444 emit(cond | s | dst.code()*B16 | src2.code()*B8 | B7 | B4 | src1.code());
1450 Register src1,
1454 ASSERT(!dstL.is(pc) && !dstH.is(pc) && !src1.is(pc) && !src2.is(pc));
1457 src2.code()*B8 | B7 | B4 | src1.code());
1463 Register src1,
1467 ASSERT(!dstL.is(pc) && !dstH.is(pc) && !src1.is(pc) && !src2.is(pc));
1470 src2.code()*B8 | B7 | B4 | src1.code());
1476 Register src1,
1480 ASSERT(!dstL.is(pc) && !dstH.is(pc) && !src1.is(pc) && !src2.is(pc));
1483 src2.code()*B8 | B7 | B4 | src1.code());
1489 Register src1,
1493 ASSERT(!dstL.is(pc) && !dstH.is(pc) && !src1.is(pc) && !src2.is(pc));
1496 src2.code()*B8 | B7 | B4 | src1.code());
1610 Register src1,
1617 ASSERT(!src1.is(pc));
1623 emit(cond | 0x68*B20 | src1.code()*B16 | dst.code()*B12 |
1629 Register src1,
1636 ASSERT(!src1.is(pc));
1643 emit(cond | 0x68*B20 | src1.code()*B16 | dst.code()*B12 |
1669 Register src1,
1676 ASSERT(!src1.is(pc));
1685 emit(cond | 0x6E*B20 | src1.code()*B16 | dst.code()*B12 |
1797 void Assembler::strd(Register src1, Register src2,
1800 ASSERT(!src1.is(lr)); // r14.
1801 ASSERT_EQ(0, src1.code() % 2);
1802 ASSERT_EQ(src1.code() + 1, src2.code());
1804 addrmod3(cond | B7 | B6 | B5 | B4, src1, dst);
2452 const Register src1,
2459 ASSERT(!src1.is(pc) && !src2.is(pc));
2463 src1.code()*B12 | 0xB*B8 | m*B5 | B4 | vm);
2729 const DwVfpRegister src1,
2740 src1.split_code(&vn, &n);
2749 const DwVfpRegister src1,
2760 src1.split_code(&vn, &n);
2769 const DwVfpRegister src1,
2780 src1.split_code(&vn, &n);
2789 const DwVfpRegister src1,
2798 src1.split_code(&vn, &n);
2807 const DwVfpRegister src1,
2816 src1.split_code(&vn, &n);
2825 const DwVfpRegister src1,
2836 src1.split_code(&vn, &n);
2844 void Assembler::vcmp(const DwVfpRegister src1,
2852 src1.split_code(&vd, &d);
2860 void Assembler::vcmp(const DwVfpRegister src1,
2869 src1.split_code(&vd, &d);
