Lines Matching full:eth_asic_base
33 static unsigned short eth_nic_base, eth_asic_base;
121 outb(src & 0xff, eth_asic_base + _3COM_DALSB);
122 outb(src >> 8, eth_asic_base + _3COM_DAMSB);
123 outb(t503_output | _3COM_CR_START, eth_asic_base + _3COM_CR);
131 while((inb(eth_asic_base + _3COM_STREG) & _3COM_STREG_DPRDY) == 0)
136 *((unsigned short *)dst) = inw(eth_asic_base + ASIC_PIO);
140 *(dst++) = inb(eth_asic_base + ASIC_PIO);
144 outb(t503_output, eth_asic_base + _3COM_CR);
168 outb(dst & 0xff, eth_asic_base + _3COM_DALSB);
169 outb(dst >> 8, eth_asic_base + _3COM_DAMSB);
171 outb(t503_output | _3COM_CR_DDIR | _3COM_CR_START, eth_asic_base + _3COM_CR);
180 while((inb(eth_asic_base + _3COM_STREG) & _3COM_STREG_DPRDY) == 0)
185 outw(*((unsigned short *)src), eth_asic_base + ASIC_PIO);
189 outb(*(src++), eth_asic_base + ASIC_PIO);
193 outb(t503_output, eth_asic_base + _3COM_CR);
280 outb(t503_output, eth_asic_base + _3COM_CR);
362 outb(eth_laar | WD_LAAR_M16EN, eth_asic_base + WD_LAAR);
366 outb(WD_MSR_MENB, eth_asic_base + WD_MSR);
378 outb(0, eth_asic_base + WD_MSR);
382 outb(eth_laar & ~WD_LAAR_M16EN, eth_asic_base + WD_LAAR);
458 outb(eth_laar | WD_LAAR_M16EN, eth_asic_base + WD_LAAR);
462 outb(WD_MSR_MENB, eth_asic_base + WD_MSR);
503 outb(0, eth_asic_base + WD_MSR);
507 outb(eth_laar & ~WD_LAAR_M16EN, eth_asic_base + WD_LAAR);
547 for (eth_asic_base = WD_LOW_BASE; eth_asic_base <= WD_HIGH_BASE;
548 eth_asic_base += 0x20) {
551 chksum += inb(eth_asic_base+i);
554 inb(eth_asic_base+8) != 0xFF &&
555 inb(eth_asic_base+9) != 0xFF)
558 if (eth_asic_base > WD_HIGH_BASE)
562 eth_nic_base = eth_asic_base + WD_NIC_ADDR;
563 c = inb(eth_asic_base+WD_BID); /* Get board id */
575 (inb(eth_asic_base + WD_ICR) & WD_ICR_16BIT)) {
581 ((inb(eth_asic_base + WD_MSR) & 0x3F) << 13));
591 outb(0x80, eth_asic_base + WD_MSR); /* Reset */
593 nic->node_addr[i] = inb(i+eth_asic_base+WD_LAR);
596 brd->name, eth_asic_base, eth_bmem, nic->node_addr);
598 outb(WD_MSR_MENB, eth_asic_base+WD_MSR);
599 outb((inb(eth_asic_base+0x04) |
600 0x80), eth_asic_base+0x04);
603 (inb(eth_asic_base+0x0B) & 0xB0), eth_asic_base+0x0B);
604 outb((inb(eth_asic_base+0x04) &
605 ~0x80), eth_asic_base+0x04);
607 outb((((unsigned)eth_bmem >> 13) & 0x3F) | 0x40, eth_asic_base+WD_MSR);
611 eth_laar = inb(eth_asic_base + WD_LAAR);
612 outb(WD_LAAR_M16EN, eth_asic_base + WD_LAAR);
615 WD_LAAR_L16EN | 1), eth_asic_base + WD_LAAR);
643 eth_asic_base = eth_nic_base + _3COM_ASIC_OFFSET;
656 iobase_reg = inb(eth_asic_base + _3COM_BCFR);
657 membase_reg = inb(eth_asic_base + _3COM_PCFR);
705 outb(_3COM_CR_RST | _3COM_CR_XSEL, eth_asic_base + _3COM_CR );
706 outb(_3COM_CR_XSEL, eth_asic_base + _3COM_CR );
710 outb(_3COM_CR_EALO | _3COM_CR_XSEL, eth_asic_base + _3COM_CR);
721 outb(_3COM_CR_XSEL, eth_asic_base + _3COM_CR);
727 _3COM_GACFR_MBS0 | _3COM_GACFR_TCM | _3COM_GACFR_NIM, eth_asic_base + _3COM_GACFR);
729 outb(0xff, eth_asic_base + _3COM_VPTR2);
730 outb(0xff, eth_asic_base + _3COM_VPTR1);
731 outb(0x00, eth_asic_base + _3COM_VPTR0);
747 outb(eth_tx_start, eth_asic_base + _3COM_PSTR);
748 outb(eth_memsize, eth_asic_base + _3COM_PSPR);
770 eth_asic_base = eth_nic_base + NE_ASIC_OFFSET;
774 c = inb(eth_asic_base + NE_RESET);
775 outb(c, eth_asic_base + NE_RESET);
