Lines Matching full:outs
761 def LDrr : F3_1 <3, 0b000000, (outs IntRegs:$dst), (ins MEMrr:$addr),
789 def LDri : F3_2 <3, 0b000000, (outs IntRegs:$dst), (ins MEMri:$addr),
804 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
808 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
857 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
866 class InstSP<dag outs, dag ins, string asmstr, list<dag> pattern> : Instruction {
871 dag OutOperandList = outs;
881 class F3<dag outs, dag ins, string asmstr, list<dag> pattern>
882 : InstSP<outs, ins, asmstr, pattern> {
898 class F3_1<bits<2> opVal, bits<6> op3val, dag outs, dag ins,
899 string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
1167 def STrr : F3_1< 3, 0b000100, (outs), (ins MEMrr:$addr, IntRegs:$src),
