Lines Matching refs:UseIdx
2867 unsigned UseIdx, unsigned UseAlign) const {
2868 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
2870 return ItinData->getOperandCycle(UseClass, UseIdx);
2907 unsigned UseIdx, unsigned UseAlign) const {
2908 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
2910 return ItinData->getOperandCycle(UseClass, UseIdx);
2937 unsigned UseIdx, unsigned UseAlign) const {
2941 if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands())
2942 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
2992 UseCycle = ItinData->getOperandCycle(UseClass, UseIdx);
3001 UseCycle = getVSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
3019 UseCycle = getSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
3033 UseClass, UseIdx))
3036 UseClass, UseIdx)) {
3070 unsigned &UseIdx, unsigned &Dist) {
3093 UseIdx = Idx;
3284 unsigned UseIdx) const {
3313 UseIdx = NewUseIdx;
3344 if (DefMO.isImplicit() || UseMI->getOperand(UseIdx).isImplicit())
3354 *UseMCID, UseIdx, UseAlign);
3374 SDNode *UseNode, unsigned UseIdx) const {
3402 UseMCID, UseIdx, UseAlign);
3657 const MachineInstr *UseMI, unsigned UseIdx) const {
3666 int Latency = computeOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx);
