Lines Matching full:outs
21 def rr : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
25 def ri : ALU32_ri<(outs IntRegs:$dst), (ins s10Imm:$b, IntRegs:$c),
34 def rr : ALU64_rr<(outs PredRegs:$dst), (ins DoubleRegs:$b, DoubleRegs:$c),
43 def rr : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
50 def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, s10Ext:$c),
60 def rr : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
67 def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, u9Ext:$c),
76 def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, s8Ext:$c),
98 def NAME : ALU32_rr<(outs RC:$dst),
117 def NAME : ALU32_rr<(outs IntRegs:$dst),
141 class T_Combine : ALU32_rr<(outs DoubleRegs:$dst),
162 ALU32_ii<(outs DoubleRegs:$dst), (ins imm1:$src1, imm2:$src2),
175 def NAME : ALU32_ri<(outs IntRegs:$dst),
195 def NAME : ALU32_ri<(outs IntRegs:$dst),
213 def OR_ri : ALU32_ri<(outs IntRegs:$dst),
221 def AND_ri : ALU32_ri<(outs IntRegs:$dst),
229 def NOP : ALU32_rr<(outs), (ins),
236 def SUB_ri : ALU32_ri<(outs IntRegs:$dst),
251 def _c#NAME : ALU32_rr<(outs IntRegs:$dst),
257 def _cdn#NAME : ALU32_rr<(outs IntRegs:$dst),
268 def NAME : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
280 : ALU32_rr<(outs DoubleRegs:$dst),
314 def NAME : ALU32Inst <(outs DoubleRegs:$dst),
338 def _c#NAME : ALU32_ri<(outs IntRegs:$dst),
345 def _cdn#NAME : ALU32_rr<(outs IntRegs:$dst),
357 def NAME : ALU32_ri<(outs IntRegs:$dst), (ins s16Ext:$src1),
375 def TFCR : CRInst<(outs CRRegs:$dst), (ins IntRegs:$src1),
388 def COMBINE_ii : ALU32_ii<(outs DoubleRegs:$dst),
394 def VMUX_prr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins PredRegs:$src1,
401 def MUX_rr : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1,
410 def MUX_ir : ALU32_ir<(outs IntRegs:$dst), (ins PredRegs:$src1, s8Ext:$src2,
419 def MUX_ri : ALU32_ri<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2,
427 def MUX_ii : ALU32_ii<(outs IntRegs:$dst), (ins PredRegs:$src1, s8Ext:$src2,
437 def NAME : ALU32Inst<(outs IntRegs:$dst),
455 def NAME : ALU32Inst<(outs IntRegs:$dst),
514 def CTLZ_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1),
518 def CTTZ_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1),
522 def CTLZ64_rr : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1),
526 def CTTZ64_rr : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1),
530 def TSTBIT_rr : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
535 def TSTBIT_ri : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
549 def ADD64_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
563 def AND_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
569 def OR_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
575 def XOR_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
582 def MAXw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
589 def MAXUw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
596 def MAXd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
605 def MAXUd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
615 def MINw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
622 def MINUw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
629 def MINd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
638 def MINUd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
648 def SUB64_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
686 def AND_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1, PredRegs:$src2),
692 def AND_pnotp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1,
697 def ANY_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1),
701 def ALL_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1),
705 def VITPACK_pp : SInst<(outs IntRegs:$dst), (ins PredRegs:$src1,
710 def VALIGN_rrp : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
716 def VSPLICE_rrp : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
722 def MASK_p : SInst<(outs DoubleRegs:$dst), (ins PredRegs:$src1),
726 def NOT_p : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1),
730 def OR_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1, PredRegs:$src2),
735 def XOR_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1, PredRegs:$src2),
758 : JInst<(outs), InsDag,
772 JInst<(outs ), (ins PredRegs:$src, brtarget:$dst),
798 : JRInst<(outs ), InsDag,
810 JRInst <(outs ), (ins PredRegs:$src, IntRegs:$dst),
906 def NAME : LDInst2<(outs RC:$dst),
928 def NAME : LDInst2<(outs RC:$dst), (ins MEMri:$addr),
981 def NAME : LDInst2<(outs RC:$dst),
1005 def NAME : LDInst2<(outs RC:$dst), (ins IntRegs:$src1, ImmOp:$offset),
1066 def NAME : LDInst2PI<(outs RC:$dst, IntRegs:$dst2),
1089 def NAME : LDInst2PI<(outs RC:$dst, IntRegs:$dst2),
1147 def LDriw_pred : LDInst2<(outs PredRegs:$dst),
1154 def DEALLOCFRAME : LDInst2<(outs), (ins),
1184 def MPYI_riu : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u8Ext:$src2),
1190 def MPYI_rin : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u8Imm:$src2),
1201 def MPYI_ri : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, s9Ext:$src2),
1208 def MPYI : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1216 def MPYI_acc_ri : MInst_acc<(outs IntRegs:$dst),
1226 def MPYI_acc_rr : MInst_acc<(outs IntRegs:$dst),
1236 def MPYI_sub_ri : MInst_acc<(outs IntRegs:$dst),
1248 def MPY : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1255 def MPYU : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1262 def MPYU64 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1269 def MPY64 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1278 def MPY64_acc : MInst_acc<(outs DoubleRegs:$dst),
1288 def MPY64_sub : MInst_acc<(outs DoubleRegs:$dst),
1299 def MPYU64_acc : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
1308 def MPYU64_sub : MInst_acc<(outs DoubleRegs:$dst),
1319 def ADDrr_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1329 def ADDri_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1338 def SUBrr_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1348 def SUBri_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1394 def NAME : STInst2PI<(outs IntRegs:$dst),
1418 def NAME : STInst2PI<(outs IntRegs:$dst),
1459 def NAME : STInst2<(outs),
1483 def NAME : STInst2<(outs),
1530 def NAME : STInst2<(outs),
1556 def NAME : STInst2<(outs),
1613 def STriw_pred : STInst2<(outs),
1620 def ALLOCFRAME : STInst2<(outs),
1633 def NOT_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1),
1639 outs DoubleRegs:$dst), (ins IntRegs:$src1),
1650 def CLRBIT : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1656 def CLRBIT_31 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1665 def SETBIT : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1671 def SETBIT_31 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1679 def TOGBIT : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1685 def TOGBIT_31 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1694 def TFR_RsPd : SInst<(outs IntRegs:$dst), (ins PredRegs:$src1),
1698 def TFR_PdRs : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1),
1709 def ASR_ri : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1714 def ASRd_ri : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
1719 def ASL : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1724 def ASLd_ri : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
1729 def LSR_ri : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1734 def LSRd_ri : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
1741 def ADDASL : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
1749 def ASL_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1754 def ASR_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1759 def LSL_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1764 def LSR_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1769 def ASLd : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
1774 def LSLd : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
1779 def ASRd_rr : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
1785 def LSRd_rr : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
1821 def BARRIER : SYSInst<(outs), (ins),
1831 def TFRI64 : ALU64_rr<(outs DoubleRegs:$dst), (ins s8Imm64:$src1),
1840 def TFR_condset_rr : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1,
1849 def TFR_condset_ri : ALU32_rr<(outs IntRegs:$dst),
1857 def TFR_condset_ir : ALU32_rr<(outs IntRegs:$dst),
1865 def TFR_condset_ii : ALU32_rr<(outs IntRegs:$dst),
1874 def TFR_FI : ALU32_ri<(outs IntRegs:$dst), (ins FrameIndex:$src1),
1882 def LOOP0_i : CRInst<(outs), (ins brtarget:$offset, u10Imm:$src2),
1888 def LOOP0_r : CRInst<(outs), (ins brtarget:$offset, IntRegs:$src2),
1895 def ENDLOOP0 : Endloop<(outs), (ins brtarget:$offset),
1911 def LO : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
1916 def HI : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
1921 def LOi : ALU32_ri<(outs IntRegs:$dst), (ins i32imm:$imm_value),
1927 def HIi : ALU32_ri<(outs IntRegs:$dst), (ins i32imm:$imm_value),
1932 def LO_jt : ALU32_ri<(outs IntRegs:$dst), (ins jumptablebase:$jt),
1937 def HI_jt : ALU32_ri<(outs IntRegs:$dst), (ins jumptablebase:$jt),
1943 def LO_label : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label),
1948 def HI_label : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label),
1956 def CONST32 : LDInst<(outs IntRegs:$dst), (ins globaladdress:$global),
1963 def CONST32_set : LDInst2<(outs IntRegs:$dst), (ins globaladdress:$global),
1969 def CONST32_set_jt : LDInst2<(outs IntRegs:$dst), (ins jumptablebase:$jt),
1975 def CONST32GP_set : LDInst2<(outs IntRegs:$dst), (ins globaladdress:$global),
1981 def CONST32_Int_Real : LDInst2<(outs IntRegs:$dst), (ins i32imm:$global),
1990 def CONST32_Label : LDInst2<(outs IntRegs:$dst), (ins bblabel:$label),
1995 def CONST64_Int_Real : LDInst2<(outs DoubleRegs:$dst), (ins i64imm:$global),
1999 def TFR_PdFalse : SInst<(outs PredRegs:$dst), (ins),
2003 outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2034 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
2040 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
2048 def CALL : JInst<(outs), (ins calltarget:$dst),
2056 def CALLR : JRInst<(outs), (ins IntRegs:$dst),
2721 def ADJDYNALLOC : ALU32_ri<(outs IntRegs:$dst), (ins IntRegs:$src1,
2730 def ARGEXTEND : ALU32_rr <(outs IntRegs:$dst), (ins IntRegs:$src1),
2749 def _ri : SInst_acc<(outs IntRegs:$dst),
2758 def d_ri : SInst_acc<(outs DoubleRegs:$dst),
2769 def _rr : SInst_acc<(outs IntRegs:$dst),
2778 def d_rr : SInst_acc<(outs DoubleRegs:$dst),
