Lines Matching full:outs
2 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1),
7 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1),
12 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1),
17 : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1),
22 : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1),
27 : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1),
32 : SInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1),
37 : SInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1),
42 : SInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1),
47 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1),
52 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1),
58 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1),
63 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
68 : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
73 : ALU64_rr<(outs PredRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
78 : ALU64_ri<(outs PredRegs:$dst), (ins DoubleRegs:$src1, u5Imm:$src2),
84 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
93 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
103 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
112 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
121 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
130 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2,
139 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2,
149 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
158 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2,
167 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2,
176 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
181 : MInst<(outs PredRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
186 : ALU64_ri<(outs IntRegs:$dst), (ins u10Imm:$src1),
191 : ALU64_ri<(outs IntRegs:$dst), (ins u10Imm:$src1),
196 : ALU64_ri<(outs DoubleRegs:$dst), (ins u10Imm:$src1),
201 : ALU64_ri<(outs DoubleRegs:$dst), (ins u10Imm:$src1),
206 : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
211 : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u4Imm:$src2),
216 : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, u4Imm:$src2),
221 : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, u4Imm:$src2),
