Lines Matching full:shiftamt
1019 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
1062 // sll shiftamt,ptrlsb2,3
1064 // sll mask,maskupper,shiftamt
1066 // sll incr2,incr,shiftamt
1075 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1080 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1085 .addReg(MaskUpper).addReg(ShiftAmt);
1087 BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt);
1139 // srl srlres,maskedoldval1,shiftamt
1148 .addReg(MaskedOldVal1).addReg(ShiftAmt);
1262 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
1310 // sll shiftamt,ptrlsb2,3
1312 // sll mask,maskupper,shiftamt
1315 // sll shiftedcmpval,maskedcmpval,shiftamt
1317 // sll shiftednewval,maskednewval,shiftamt
1325 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1330 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1335 .addReg(MaskUpper).addReg(ShiftAmt);
1340 .addReg(MaskedCmpVal).addReg(ShiftAmt);
1344 .addReg(MaskedNewVal).addReg(ShiftAmt);
1373 // srl srlres,maskedoldval0,shiftamt
1380 .addReg(MaskedOldVal0).addReg(ShiftAmt);
