Lines Matching refs:NOR
923 unsigned LL, SC, AND, NOR, ZERO, BEQ;
929 NOR = Mips::NOR;
937 NOR = Mips::NOR64;
981 // nor storeval, $0, andres
983 BuildMI(BB, DL, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes);
1065 // nor mask2,$0,mask
1086 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1112 // nor binopres, $0, andres
1115 BuildMI(BB, DL, TII->get(Mips::NOR), BinOpRes)
1313 // nor mask2,$0,mask
1336 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1977 // Return if load is aligned or if MemVT is neither i32 nor i64.
