Lines Matching full:outs
17 def NOP : NVPTXInst<(outs), (ins), "", []>;
170 def i64rr : NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$a, Int64Regs:$b),
174 def i64ri : NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$a, i64imm:$b),
177 def i32rr : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a, Int32Regs:$b),
181 def i32ri : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a, i32imm:$b),
184 def i16rr : NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$a, Int16Regs:$b),
188 def i16ri : NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$a, i16imm:$b),
194 def i32rr : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a,
199 def i32ri : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a, i32imm:$b),
205 def f64rr : NVPTXInst<(outs Float64Regs:$dst),
211 def f64ri : NVPTXInst<(outs Float64Regs:$dst),
217 def f32rr_ftz : NVPTXInst<(outs Float32Regs:$dst),
223 def f32ri_ftz : NVPTXInst<(outs Float32Regs:$dst),
229 def f32rr : NVPTXInst<(outs Float32Regs:$dst),
235 def f32ri : NVPTXInst<(outs Float32Regs:$dst),
244 def f64rr : NVPTXInst<(outs Float64Regs:$dst),
249 def f64ri : NVPTXInst<(outs Float64Regs:$dst),
254 def f32rr_ftz : NVPTXInst<(outs Float32Regs:$dst),
260 def f32ri_ftz : NVPTXInst<(outs Float32Regs:$dst),
266 def f32rr : NVPTXInst<(outs Float32Regs:$dst),
271 def f32ri : NVPTXInst<(outs Float32Regs:$dst),
279 def f64 : NVPTXInst<(outs Float64Regs:$dst), (ins Float64Regs:$a),
282 def f32_ftz : NVPTXInst<(outs Float32Regs:$dst), (ins Float32Regs:$a),
286 def f32 : NVPTXInst<(outs Float32Regs:$dst), (ins Float32Regs:$a),
304 def _s16 : NVPTXInst<(outs RC:$dst),
309 def _u16 : NVPTXInst<(outs RC:$dst),
314 def _f16 : NVPTXInst<(outs RC:$dst),
319 def _s32 : NVPTXInst<(outs RC:$dst),
324 def _u32 : NVPTXInst<(outs RC:$dst),
329 def _s64 : NVPTXInst<(outs RC:$dst),
334 def _u64 : NVPTXInst<(outs RC:$dst),
339 def _f32 : NVPTXInst<(outs RC:$dst),
344 def _f64 : NVPTXInst<(outs RC:$dst),
365 def CVT_INREG_s16_s8 : NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$src),
367 def CVT_INREG_s32_s8 : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$src),
369 def CVT_INREG_s32_s16 : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$src),
371 def CVT_INREG_s64_s8 : NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$src),
373 def CVT_INREG_s64_s16 : NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$src),
375 def CVT_INREG_s64_s32 : NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$src),
384 def _rr: NVPTXInst<(outs Int1Regs:$dst), (ins Int1Regs:$a, Int1Regs:$b),
387 def _ri: NVPTXInst<(outs Int1Regs:$dst), (ins Int1Regs:$a, i1imm:$b),
464 def MULWIDES64 : NVPTXInst<(outs Int64Regs:$dst),
467 def MULWIDES64Imm : NVPTXInst<(outs Int64Regs:$dst),
471 def MULWIDEU64 : NVPTXInst<(outs Int64Regs:$dst),
474 def MULWIDEU64Imm : NVPTXInst<(outs Int64Regs:$dst),
478 def MULWIDES32 : NVPTXInst<(outs Int32Regs:$dst),
481 def MULWIDES32Imm : NVPTXInst<(outs Int32Regs:$dst),
485 def MULWIDEU32 : NVPTXInst<(outs Int32Regs:$dst),
488 def MULWIDEU32Imm : NVPTXInst<(outs Int32Regs:$dst),
544 def MAD16rrr : NVPTXInst<(outs Int16Regs:$dst),
549 def MAD16rri : NVPTXInst<(outs Int16Regs:$dst),
554 def MAD16rir : NVPTXInst<(outs Int16Regs:$dst),
559 def MAD16rii : NVPTXInst<(outs Int16Regs:$dst),
565 def MAD32rrr : NVPTXInst<(outs Int32Regs:$dst),
570 def MAD32rri : NVPTXInst<(outs Int32Regs:$dst),
575 def MAD32rir : NVPTXInst<(outs Int32Regs:$dst),
580 def MAD32rii : NVPTXInst<(outs Int32Regs:$dst),
586 def MAD64rrr : NVPTXInst<(outs Int64Regs:$dst),
591 def MAD64rri : NVPTXInst<(outs Int64Regs:$dst),
596 def MAD64rir : NVPTXInst<(outs Int64Regs:$dst),
601 def MAD64rii : NVPTXInst<(outs Int64Regs:$dst),
608 def INEG16 : NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$src),
611 def INEG32 : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$src),
614 def INEG64 : NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$src),
652 def FDIV641r : NVPTXInst<(outs Float64Regs:$dst),
657 def FDIV64rr : NVPTXInst<(outs Float64Regs:$dst),
662 def FDIV64ri : NVPTXInst<(outs Float64Regs:$dst),
671 def FDIV321r_ftz : NVPTXInst<(outs Float32Regs:$dst),
677 def FDIV321r : NVPTXInst<(outs Float32Regs:$dst),
686 def FDIV32approxrr_ftz : NVPTXInst<(outs Float32Regs:$dst),
692 def FDIV32approxrr : NVPTXInst<(outs Float32Regs:$dst),
703 def FDIV321r_approx_ftz : NVPTXInst<(outs Float32Regs:$dst),
709 def FDIV321r_approx : NVPTXInst<(outs Float32Regs:$dst),
718 def FDIV32rr_ftz : NVPTXInst<(outs Float32Regs:$dst),
724 def FDIV32ri_ftz : NVPTXInst<(outs Float32Regs:$dst),
730 def FDIV32rr : NVPTXInst<(outs Float32Regs:$dst),
736 def FDIV32ri : NVPTXInst<(outs Float32Regs:$dst),
745 def FDIV321r_prec_ftz : NVPTXInst<(outs Float32Regs:$dst),
751 def FDIV321r_prec : NVPTXInst<(outs Float32Regs:$dst),
760 def FDIV32rr_prec_ftz : NVPTXInst<(outs Float32Regs:$dst),
766 def FDIV32ri_prec_ftz : NVPTXInst<(outs Float32Regs:$dst),
772 def FDIV32rr_prec : NVPTXInst<(outs Float32Regs:$dst),
778 def FDIV32ri_prec : NVPTXInst<(outs Float32Regs:$dst),
789 def RSQRTF32approx1r : NVPTXInst<(outs Float32Regs:$dst), (ins Float32Regs:$b),
797 def rrr : NVPTXInst<(outs Float32Regs:$dst),
807 def rrr2 : NVPTXInst<(outs Float32Regs:$dst),
813 def rri : NVPTXInst<(outs Float32Regs:$dst),
819 def rir : NVPTXInst<(outs Float32Regs:$dst),
825 def rii : NVPTXInst<(outs Float32Regs:$dst),
834 def rrr : NVPTXInst<(outs Float64Regs:$dst),
840 def rri : NVPTXInst<(outs Float64Regs:$dst),
845 def rir : NVPTXInst<(outs Float64Regs:$dst),
851 def rii : NVPTXInst<(outs Float64Regs:$dst),
905 def SINF: NVPTXInst<(outs Float32Regs:$dst), (ins Float32Regs:$src),
908 def COSF: NVPTXInst<(outs Float32Regs:$dst), (ins Float32Regs:$src),
952 def b1rr: NVPTXInst<(outs Int1Regs:$dst), (ins Int1Regs:$a, Int1Regs:$b),
955 def b1ri: NVPTXInst<(outs Int1Regs:$dst), (ins Int1Regs:$a, i1imm:$b),
958 def b16rr: NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$a, Int16Regs:$b),
962 def b16ri: NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$a, i16imm:$b),
965 def b32rr: NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a, Int32Regs:$b),
969 def b32ri: NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a, i32imm:$b),
972 def b64rr: NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$a, Int64Regs:$b),
976 def b64ri: NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$a, i64imm:$b),
985 def NOT1: NVPTXInst<(outs Int1Regs:$dst), (ins Int1Regs:$src),
988 def NOT16: NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$src),
991 def NOT32: NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$src),
994 def NOT64: NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$src),
1000 def i64rr : NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$a,
1005 def i64ri : NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$a, i32imm:$b),
1009 def i32rr : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a,
1014 def i32ri : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a, i32imm:$b),
1018 def i32ii : NVPTXInst<(outs Int32Regs:$dst), (ins i32imm:$a, i32imm:$b),
1022 def i16rr : NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$a,
1027 def i16ri : NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$a, i32imm:$b),
1038 def i64rr : NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$a,
1043 def i64ri : NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$a, i32imm:$b),
1047 def i32rr : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a,
1052 def i32ri : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a, i32imm:$b),
1056 def i32ii : NVPTXInst<(outs Int32Regs:$dst), (ins i32imm:$a, i32imm:$b),
1060 def i16rr : NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$a,
1065 def i16ri : NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$a, i32imm:$b),
1075 def ROT32imm_sw : NVPTXInst<(outs Int32Regs:$dst),
1095 def ROTL32reg_sw : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$src,
1108 def ROTR32reg_sw : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$src,
1122 def ROT64imm_sw : NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$src,
1142 def ROTL64reg_sw : NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$src,
1155 def ROTR64reg_sw : NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$src,
1175 def rr : NVPTXInst<(outs Int1Regs:$dst),
1179 def ri : NVPTXInst<(outs Int1Regs:$dst),
1183 def ir : NVPTXInst<(outs Int1Regs:$dst),
1203 def rr : NVPTXInst<(outs Int32Regs:$dst),
1206 def ri : NVPTXInst<(outs Int32Regs:$dst),
1209 def ir : NVPTXInst<(outs Int32Regs:$dst),
1232 def rr : NVPTXInst<(outs RC:$dst),
1235 def ri : NVPTXInst<(outs RC:$dst),
1238 def ir : NVPTXInst<(outs RC:$dst),
1241 def ii : NVPTXInst<(outs RC:$dst),
1248 def rr : NVPTXInst<(outs RC:$dst),
1252 def ri : NVPTXInst<(outs RC:$dst),
1256 def ir : NVPTXInst<(outs RC:$dst),
1260 def ii : NVPTXInst<(outs RC:$dst),
1316 def MOV_ADDR : NVPTXInst<(outs Int32Regs:$dst), (ins imem:$a),
1320 def MOV_ADDR64 : NVPTXInst<(outs Int64Regs:$dst), (ins imem:$a),
1326 : NVPTXInst<(outs Int32Regs:$d), (ins i32imm:$num),
1329 : NVPTXInst<(outs Int64Regs:$d), (ins i32imm:$num),
1335 def IMOV1rr: NVPTXInst<(outs Int1Regs:$dst), (ins Int1Regs:$sss),
1337 def IMOV16rr: NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$sss),
1339 def IMOV32rr: NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$sss),
1341 def IMOV64rr: NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$sss),
1344 def FMOV32rr: NVPTXInst<(outs Float32Regs:$dst), (ins Float32Regs:$src),
1346 def FMOV64rr: NVPTXInst<(outs Float64Regs:$dst), (ins Float64Regs:$src),
1349 def IMOV1ri: NVPTXInst<(outs Int1Regs:$dst), (ins i1imm:$src),
1352 def IMOV16ri: NVPTXInst<(outs Int16Regs:$dst), (ins i16imm:$src),
1355 def IMOV32ri: NVPTXInst<(outs Int32Regs:$dst), (ins i32imm:$src),
1358 def IMOV64i: NVPTXInst<(outs Int64Regs:$dst), (ins i64imm:$src),
1362 def FMOV32ri: NVPTXInst<(outs Float32Regs:$dst), (ins f32imm:$src),
1365 def FMOV64ri: NVPTXInst<(outs Float64Regs:$dst), (ins f64imm:$src),
1372 def LEA_ADDRi : NVPTXInst<(outs Int32Regs:$dst), (ins MEMri:$addr),
1375 def LEA_ADDRi64 : NVPTXInst<(outs Int64Regs:$dst), (ins MEMri64:$addr),
1657 NVPTXInst<(outs regclass:$dst), (ins i32imm:$b),
1663 NVPTXInst<(outs regclass:$dst), (ins i32imm:$b),
1669 NVPTXInst<(outs regclass:$dst, regclass:$dst2), (ins i32imm:$b),
1674 NVPTXInst<(outs regclass:$dst, regclass:$dst2, regclass:$dst3,
1681 NVPTXInst<(outs), (ins regclass:$val, i32imm:$a, i32imm:$b),
1687 NVPTXInst<(outs), (ins regclass:$val, regclass:$val2,
1694 NVPTXInst<(outs), (ins regclass:$val, regclass:$val1, regclass:$val2,
1701 NVPTXInst<(outs), (ins regclass:$val, i32imm:$a),
1707 NVPTXInst<(outs), (ins regclass:$val, regclass:$val2, i32imm:$a),
1713 NVPTXInst<(outs),
1720 def PrintCallRetInst1 : NVPTXInst<(outs), (ins),
1723 def PrintCallRetInst2 : NVPTXInst<(outs), (ins),
1726 def PrintCallRetInst3 : NVPTXInst<(outs), (ins),
1729 def PrintCallRetInst4 : NVPTXInst<(outs), (ins),
1732 def PrintCallRetInst5 : NVPTXInst<(outs), (ins),
1735 def PrintCallRetInst6 : NVPTXInst<(outs), (ins),
1738 def PrintCallRetInst7 : NVPTXInst<(outs), (ins),
1741 def PrintCallRetInst8 : NVPTXInst<(outs), (ins),
1746 def PrintCallNoRetInst : NVPTXInst<(outs), (ins), "call ",
1749 def PrintCallUniRetInst1 : NVPTXInst<(outs), (ins),
1752 def PrintCallUniRetInst2 : NVPTXInst<(outs), (ins),
1755 def PrintCallUniRetInst3 : NVPTXInst<(outs), (ins),
1758 def PrintCallUniRetInst4 : NVPTXInst<(outs), (ins),
1761 def PrintCallUniRetInst5 : NVPTXInst<(outs), (ins),
1764 def PrintCallUniRetInst6 : NVPTXInst<(outs), (ins),
1767 def PrintCallUniRetInst7 : NVPTXInst<(outs), (ins),
1770 def PrintCallUniRetInst8 : NVPTXInst<(outs), (ins),
1775 def PrintCallUniNoRetInst : NVPTXInst<(outs), (ins), "call.uni ",
1807 def StoreParamV4I32 : NVPTXInst<(outs), (ins Int32Regs:$val, Int32Regs:$val2,
1813 def StoreParamV4I16 : NVPTXInst<(outs), (ins Int16Regs:$val, Int16Regs:$val2,
1819 def StoreParamV4I8 : NVPTXInst<(outs), (ins Int16Regs:$val, Int16Regs:$val2,
1831 def StoreParamV4F32 : NVPTXInst<(outs),
1857 def CallArgBeginInst : NVPTXInst<(outs), (ins), "(", [(CallArgBegin)]>;
1858 def CallArgEndInst1 : NVPTXInst<(outs), (ins), ");", [(CallArgEnd (i32 1))]>;
1859 def CallArgEndInst0 : NVPTXInst<(outs), (ins), ")", [(CallArgEnd (i32 0))]>;
1860 def RETURNInst : NVPTXInst<(outs), (ins), "ret;", [(RETURNNode)]>;
1863 NVPTXInst<(outs), (ins regclass:$a), "$a, ",
1867 NVPTXInst<(outs), (ins regclass:$a), "$a",
1884 def CallArgI32imm : NVPTXInst<(outs), (ins i32imm:$a), "$a, ",
1886 def LastCallArgI32imm : NVPTXInst<(outs), (ins i32imm:$a), "$a",
1889 def CallArgParam : NVPTXInst<(outs), (ins i32imm:$a), "param$a, ",
1891 def LastCallArgParam : NVPTXInst<(outs), (ins i32imm:$a), "param$a",
1894 def CallVoidInst : NVPTXInst<(outs), (ins imem:$addr),
1897 def CallVoidInstReg : NVPTXInst<(outs), (ins Int32Regs:$addr),
1900 def CallVoidInstReg64 : NVPTXInst<(outs), (ins Int64Regs:$addr),
1903 def PrototypeInst : NVPTXInst<(outs), (ins i32imm:$val),
1907 def DeclareRetMemInst : NVPTXInst<(outs),
1911 def DeclareRetScalarInst : NVPTXInst<(outs), (ins i32imm:$size, i32imm:$num),
1914 def DeclareRetRegInst : NVPTXInst<(outs), (ins i32imm:$size, i32imm:$num),
1918 def DeclareParamInst : NVPTXInst<(outs),
1922 def DeclareScalarParamInst : NVPTXInst<(outs), (ins i32imm:$a, i32imm:$size),
1925 def DeclareScalarRegInst : NVPTXInst<(outs), (ins i32imm:$a, i32imm:$size),
1930 NVPTXInst<(outs regclass:$dst), (ins regclass:$src),
1936 def MoveParamI16 : NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$src),
1943 NVPTXInst<(outs), (ins regclass:$src),
1958 def _avar : NVPTXInst<(outs regclass:$dst),
1963 def _areg : NVPTXInst<(outs regclass:$dst),
1968 def _areg_64 : NVPTXInst<(outs regclass:$dst),
1973 def _ari : NVPTXInst<(outs regclass:$dst),
1978 def _ari_64 : NVPTXInst<(outs regclass:$dst),
1983 def _asi : NVPTXInst<(outs regclass:$dst),
2000 def _avar : NVPTXInst<(outs),
2005 def _areg : NVPTXInst<(outs),
2010 def _areg_64 : NVPTXInst<(outs),
2015 def _ari : NVPTXInst<(outs),
2020 def _ari_64 : NVPTXInst<(outs),
2025 def _asi : NVPTXInst<(outs),
2046 def _v2_avar : NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
2051 def _v2_areg : NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
2056 def _v2_areg_64 : NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
2061 def _v2_ari : NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
2066 def _v2_ari_64 : NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
2071 def _v2_asi : NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
2076 def _v4_avar : NVPTXInst<(outs regclass:$dst1, regclass:$dst2,
2082 def _v4_areg : NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
2088 def _v4_areg_64 : NVPTXInst<(outs regclass:$dst1, regclass:$dst2,
2094 def _v4_ari : NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
2101 def _v4_ari_64 : NVPTXInst<(outs regclass:$dst1, regclass:$dst2,
2108 def _v4_asi : NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
2126 def _v2_avar : NVPTXInst<(outs),
2131 def _v2_areg : NVPTXInst<(outs),
2136 def _v2_areg_64 : NVPTXInst<(outs),
2141 def _v2_ari : NVPTXInst<(outs),
2147 def _v2_ari_64 : NVPTXInst<(outs),
2153 def _v2_asi : NVPTXInst<(outs),
2159 def _v4_avar : NVPTXInst<(outs),
2165 def _v4_areg : NVPTXInst<(outs),
2171 def _v4_areg_64 : NVPTXInst<(outs),
2177 def _v4_ari : NVPTXInst<(outs),
2184 def _v4_ari_64 : NVPTXInst<(outs),
2191 def _v4_asi : NVPTXInst<(outs),
2213 NVPTXInst<(outs regclassOut:$d), (ins regclassIn:$a),
2420 def V4I16toI64 : NVPTXInst<(outs Int64Regs:$d),
2425 def V2I16toI32 : NVPTXInst<(outs Int32Regs:$d),
2429 def V2I32toI64 : NVPTXInst<(outs Int64Regs:$d),
2433 def V2F32toF64 : NVPTXInst<(outs Float64Regs:$d),
2439 def I64toV4I16 : NVPTXInst<(outs Int16Regs:$d1, Int16Regs:$d2,
2444 def I32toV2I16 : NVPTXInst<(outs Int16Regs:$d1, Int16Regs:$d2),
2448 def I64toV2I32 : NVPTXInst<(outs Int32Regs:$d1, Int32Regs:$d2),
2452 def F64toV2F32 : NVPTXInst<(outs Float32Regs:$d1, Float32Regs:$d2),
2458 def CLZr32 : NVPTXInst<(outs Int32Regs:$d), (ins Int32Regs:$a),
2461 def CLZr64 : NVPTXInst<(outs Int32Regs:$d), (ins Int64Regs:$a),
2492 def POPCr32 : NVPTXInst<(outs Int32Regs:$d), (ins Int32Regs:$a),
2495 def POPCr64 : NVPTXInst<(outs Int32Regs:$d), (ins Int64Regs:$a),
2536 def Return : NVPTXInst<(outs), (ins), "ret;", [(retflag)]>;
2539 def CBranch : NVPTXInst<(outs), (ins Int1Regs:$a, brtarget:$target),
2543 def CBranchOther : NVPTXInst<(outs), (ins Int1Regs:$a, brtarget:$target),
2548 def GOTO : NVPTXInst<(outs), (ins brtarget:$target),
2582 def CALL : NVPTXInst<(outs), (ins calltarget:$dst),
2592 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
2593 : NVPTXInst<outs, ins, asmstr, pattern>;
2597 def Callseq_Start : NVPTXInst<(outs), (ins i32imm:$amt),
2600 def Callseq_End : NVPTXInst<(outs), (ins i32imm:$amt1, i32imm:$amt2),
2606 def trapinst : NVPTXInst<(outs), (ins),
