Lines Matching defs:VT
103 MVT::SimpleValueType VT = (MVT::SimpleValueType)types[x];
105 setOperationAction(ISD::ADD, VT, Expand);
106 setOperationAction(ISD::AND, VT, Expand);
107 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
108 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
109 setOperationAction(ISD::MUL, VT, Expand);
110 setOperationAction(ISD::OR, VT, Expand);
111 setOperationAction(ISD::SHL, VT, Expand);
112 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
113 setOperationAction(ISD::SRL, VT, Expand);
114 setOperationAction(ISD::SRA, VT, Expand);
115 setOperationAction(ISD::SUB, VT, Expand);
116 setOperationAction(ISD::UDIV, VT, Expand);
117 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
118 setOperationAction(ISD::UREM, VT, Expand);
119 setOperationAction(ISD::VSELECT, VT, Expand);
120 setOperationAction(ISD::XOR, VT, Expand);
137 bool AMDGPUTargetLowering::isFAbsFree(EVT VT) const {
138 assert(VT.isFloatingPoint());
139 return VT == MVT::f32;
142 bool AMDGPUTargetLowering::isFNegFree(EVT VT) const {
143 assert(VT.isFloatingPoint());
144 return VT == MVT::f32;
215 EVT VT = Op.getValueType();
222 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1));
226 return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1));
228 return DAG.getNode(AMDGPUISD::FMAX, DL, VT, Op.getOperand(1),
231 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Op.getOperand(1),
234 return DAG.getNode(AMDGPUISD::UMAX, DL, VT, Op.getOperand(1),
237 return DAG.getNode(AMDGPUISD::FMIN, DL, VT, Op.getOperand(1),
240 return DAG.getNode(AMDGPUISD::SMIN, DL, VT, Op.getOperand(1),
243 return DAG.getNode(AMDGPUISD::UMIN, DL, VT, Op.getOperand(1),
246 return DAG.getNode(ISD::FRINT, DL, VT, Op.getOperand(1));
255 EVT VT = Op.getValueType();
256 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
259 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Neg, Op.getOperand(1));
267 EVT VT = Op.getValueType();
268 SDValue OneSubA = DAG.getNode(ISD::FSUB, DL, VT,
271 SDValue OneSubAC = DAG.getNode(ISD::FMUL, DL, VT, OneSubA,
273 return DAG.getNode(ISD::FADD, DL, VT,
274 DAG.getNode(ISD::FMUL, DL, VT, Op.getOperand(1), Op.getOperand(2)),
282 EVT VT = Op.getValueType();
290 if (VT != MVT::f32 ||
317 return DAG.getNode(AMDGPUISD::FMIN, DL, VT, LHS, RHS);
319 return DAG.getNode(AMDGPUISD::FMAX, DL, VT, LHS, RHS);
328 return DAG.getNode(AMDGPUISD::FMAX, DL, VT, LHS, RHS);
330 return DAG.getNode(AMDGPUISD::FMIN, DL, VT, LHS, RHS);
343 EVT VT = Op.getValueType();
352 SDValue RCP = DAG.getNode(AMDGPUISD::URECIP, DL, VT, Den);
355 SDValue RCP_LO = DAG.getNode(ISD::UMULO, DL, VT, RCP, Den);
358 SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den);
361 SDValue NEG_RCP_LO = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
365 SDValue ABS_RCP_LO = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
370 SDValue E = DAG.getNode(ISD::MULHU, DL, VT, ABS_RCP_LO, RCP);
373 SDValue RCP_A_E = DAG.getNode(ISD::ADD, DL, VT, RCP, E);
376 SDValue RCP_S_E = DAG.getNode(ISD::SUB, DL, VT, RCP, E);
379 SDValue Tmp0 = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
383 SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num);
386 SDValue Num_S_Remainder = DAG.getNode(ISD::UMULO, DL, VT, Quotient, Den);
389 SDValue Remainder = DAG.getNode(ISD::SUB, DL, VT, Num, Num_S_Remainder);
393 DAG.getConstant(-1, VT),
394 DAG.getConstant(0, VT),
398 DAG.getConstant(0, VT),
399 DAG.getConstant(-1, VT),
400 DAG.getConstant(0, VT),
403 SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den,
409 SDValue Quotient_A_One = DAG.getNode(ISD::ADD, DL, VT, Quotient,
410 DAG.getConstant(1, VT));
413 SDValue Quotient_S_One = DAG.getNode(ISD::SUB, DL, VT, Quotient,
414 DAG.getConstant(1, VT));
417 SDValue Div = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
421 Div = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
427 SDValue Remainder_S_Den = DAG.getNode(ISD::SUB, DL, VT, Remainder, Den);
430 SDValue Remainder_A_Den = DAG.getNode(ISD::ADD, DL, VT, Remainder, Den);
433 SDValue Rem = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
437 Rem = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
471 unsigned Reg, EVT VT) const {
481 return DAG.getRegister(VirtualRegister, VT);
