Lines Matching defs:Reg
226 unsigned Reg = VA.getLocReg();
230 Reg = TRI->getMatchingSuperReg(Reg, AMDGPU::sub0,
232 Reg = MF.addLiveIn(Reg, &AMDGPU::SReg_64RegClass);
233 InVals.push_back(DAG.getCopyFromReg(Chain, DL, Reg, VT));
237 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
239 Reg = MF.addLiveIn(Reg, RC);
240 SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, VT);
251 Reg = ArgLocs[ArgIdx++].getLocReg();
252 Reg = MF.addLiveIn(Reg, RC);
253 Regs.push_back(DAG.getCopyFromReg(Chain, DL, Reg, VT));
686 unsigned Reg = cast<RegisterSDNode>(Op->getOperand(1))->getReg();
687 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
688 return MRI.getRegClass(Reg);
690 return TRI.getPhysRegClass(Reg);
1075 unsigned Reg, EVT VT) const {
1076 SDValue VReg = AMDGPUTargetLowering::CreateLiveInRegister(DAG, RC, Reg, VT);
