Lines Matching defs:Reg
125 unsigned Reg = MO.getReg();
126 if (!Reg)
128 for (MCRegAliasIterator AI(Reg, &TRI, true); AI.isValid(); ++AI)
167 unsigned Reg = isSub
170 if (Reg) {
175 .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub));
295 unsigned Reg = II->first;
297 if (Reg == X86::EAX || Reg == X86::AX ||
298 Reg == X86::AH || Reg == X86::AL)
337 unsigned Reg = I->getReg();
360 if (HasFP && FramePtr == Reg)
363 unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
371 static int getCompactUnwindRegNum(unsigned Reg, bool is64Bit) {
380 if (*CURegs == Reg)
471 unsigned Reg = SavedRegs[I];
472 if (Reg == 0) continue;
474 int CURegNum = getCompactUnwindRegNum(Reg, Is64Bit);
527 unsigned Reg = MI.getOperand(0).getReg();
528 if (Reg == (Is64Bit ? X86::RAX : X86::EAX)) {
731 // REG < 64 => DW_CFA_offset + Reg
1245 unsigned Reg = CSI[i-1].getReg();
1246 if (!X86::GR64RegClass.contains(Reg) &&
1247 !X86::GR32RegClass.contains(Reg))
1250 MBB.addLiveIn(Reg);
1251 if (Reg == FPReg)
1255 BuildMI(MBB, MI, DL, TII.get(Opc)).addReg(Reg, RegState::Kill)
1265 unsigned Reg = CSI[i-1].getReg();
1266 if (X86::GR64RegClass.contains(Reg) ||
1267 X86::GR32RegClass.contains(Reg))
1270 MBB.addLiveIn(Reg);
1271 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1272 TII.storeRegToStackSlot(MBB, MI, Reg, true, CSI[i-1].getFrameIdx(),
1293 unsigned Reg = CSI[i].getReg();
1294 if (X86::GR64RegClass.contains(Reg) ||
1295 X86::GR32RegClass.contains(Reg))
1297 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1298 TII.loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(),
1306 unsigned Reg = CSI[i].getReg();
1307 if (!X86::GR64RegClass.contains(Reg) &&
1308 !X86::GR32RegClass.contains(Reg))
1310 if (Reg
1313 BuildMI(MBB, MI, DL, TII.get(Opc), Reg);
