Lines Matching refs:CMOV
510 // X86 wants to expand cmov itself.
1537 // Predictable cmov don't hurt on atom because it's in-order.
3479 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3480 /// code. Current x86 isa includes the following FP cmov instructions:
5691 SDValue CmovOp = DAG.getNode(X86ISD::CMOV, dl, MVT::i16,
5699 SDValue CmovOp = DAG.getNode(X86ISD::CMOV, dl, MVT::i32,
8332 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
8333 CMOV, dl, VT, Ops1, 4);
8335 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
8336 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
10130 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
10131 // widen the cmov and push the truncate through. This avoids introducing a new
10140 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
10141 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
10145 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
10149 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
11416 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
11782 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
11834 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops));
13135 case X86ISD::CMOV: return "X86ISD::CMOV";
13626 // Get pseudo CMOV opcode from the specified data type.
13635 llvm_unreachable("Unknown CMOV opcode!");
13860 // Replace the original PHI node as mainMBB is changed after CMOV
14135 // As the lowered CMOV won't clobber EFLAGS, we could reuse it for the
14136 // 2nd CMOV lowering.
14142 // Replace the original PHI node as mainMBB is changed after CMOV
16344 // where Op could be BRCOND or CMOV.
16419 case X86ISD::CMOV: {
16463 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
16469 // If the flag operand isn't dead, don't touch this CMOV.
16497 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(),
16599 // of CMOV and CMP.
16628 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops,
17202 // Generate NEG and CMOV for integer abs.
17206 // Since X86 does not have CMOV for 8-bit integer, we don't convert
17207 // 8-bit integer abs to NEG and CMOV.
17216 // and change it to SUB and CMOV.
17224 // Generate SUB & CMOV.
17231 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue),
18357 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
