Lines Matching defs:Reg
153 unsigned Reg = MI.getOperand(0).getReg();
156 assert(XCore::GRRegsRegClass.contains(Reg) && "Unexpected register operand");
172 BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg)
178 .addReg(Reg, getKillRegState(isKill))
183 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg)
193 BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg)
199 .addReg(Reg, getKillRegState(isKill))
204 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg)
222 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
228 .addReg(Reg, getKillRegState(isKill))
233 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
