Lines Matching full:outs
26 : VOP3 <op, (outs VReg_32:$dst), (ins AllReg_32:$src0, AllReg_32:$src1, AllReg_32:$src2, i32imm:$src3, i32imm:$src4, i32imm:$src5, i32imm:$src6), opName, pattern>;
29 : VOP3 <op, (outs VReg_64:$dst), (ins AllReg_64:$src0, AllReg_64:$src1, AllReg_64:$src2, i32imm:$src3, i32imm:$src4, i32imm:$src5, i32imm:$src6), opName, pattern>;
33 : SOP1 <op, (outs SReg_32:$dst), (ins SReg_32:$src0), opName, pattern>;
36 : SOP1 <op, (outs SReg_64:$dst), (ins SReg_64:$src0), opName, pattern>;
39 : SOP2 <op, (outs SReg_32:$dst), (ins SReg_32:$src0, SReg_32:$src1), opName, pattern>;
42 : SOP2 <op, (outs SReg_64:$dst), (ins SReg_64:$src0, SReg_64:$src1), opName, pattern>;
45 : SOP2 <op, (outs VCCReg:$vcc), (ins SReg_64:$src0, SReg_64:$src1), opName, pattern>;
50 op, (outs vrc:$dst), (ins arc:$src0), opName, pattern
73 op, (outs vrc:$dst), (ins arc:$src0, vrc:$src1), opName, pattern
95 : SOPK <op, (outs SReg_32:$dst), (ins i16imm:$src0), opName, pattern>;
98 : SOPK <op, (outs SReg_64:$dst), (ins i16imm:$src0), opName, pattern>;
127 : SOPC <op, (outs SCCReg:$dst), (ins SReg_32:$src0, SReg_32:$src1), opName, pattern>;
130 : SOPC <op, (outs SCCReg:$dst), (ins SReg_64:$src0, SReg_64:$src1), opName, pattern>;
