Lines Matching refs:target_ulong
26 target_ulong VPN;
36 target_ulong PFN[2];
42 int (*map_address) (struct CPUMIPSState *env, target_phys_addr_t *physical, int *prot, target_ulong address, int rw, int access_type);
141 target_ulong gpr[32];
142 target_ulong PC;
143 target_ulong HI[MIPS_DSP_ACC];
144 target_ulong LO[MIPS_DSP_ACC];
145 target_ulong ACX[MIPS_DSP_ACC];
146 target_ulong DSPControl;
165 target_ulong CP0_TCHalt;
166 target_ulong CP0_TCContext;
167 target_ulong CP0_TCSchedule;
168 target_ulong CP0_TCScheFBack;
182 target_ulong SEGMask;
183 target_ulong PAMask;
207 target_ulong CP0_YQMask;
208 target_ulong CP0_VPESchedule;
209 target_ulong CP0_VPEScheFBack;
227 target_ulong CP0_EntryLo0;
228 target_ulong CP0_EntryLo1;
229 target_ulong CP0_Context;
263 target_ulong CP0_BadVAddr;
265 target_ulong CP0_EntryHi;
319 target_ulong CP0_EPC;
374 target_ulong lladdr;
375 target_ulong llval;
376 target_ulong llnewval;
377 target_ulong llreg;
378 target_ulong CP0_LLAddr_rw_bitmask;
380 target_ulong CP0_WatchLo[8];
382 target_ulong CP0_XContext;
403 target_ulong CP0_DEPC;
409 target_ulong CP0_ErrorEPC;
447 target_ulong btarget; /* Jump / branch target */
448 target_ulong bcond; /* Branch condition (if needed) */
456 target_ulong tls_value; /* For usermode emulation */
469 target_ulong address, int rw, int access_type);
471 target_ulong address, int rw, int access_type);
473 target_ulong address, int rw, int access_type);
512 static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
628 int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
632 target_phys_addr_t cpu_mips_translate_address (CPUState *env, target_ulong address,
642 static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
643 target_ulong *cs_base, int *flags)
650 static inline void cpu_set_tls(CPUState *env, target_ulong newtls)
