Lines Matching refs:qemu_put_sbe32s
21 qemu_put_sbe32s(f, &tc->CP0_TCStatus);
22 qemu_put_sbe32s(f, &tc->CP0_TCBind);
27 qemu_put_sbe32s(f, &tc->CP0_Debug_tcstatus);
55 qemu_put_sbe32s(f, &env->mvp->CP0_MVPControl);
56 qemu_put_sbe32s(f, &env->mvp->CP0_MVPConf0);
57 qemu_put_sbe32s(f, &env->mvp->CP0_MVPConf1);
83 qemu_put_sbe32s(f, &env->error_code);
87 qemu_put_sbe32s(f, &i);
90 qemu_put_sbe32s(f, &env->CP0_Index);
91 qemu_put_sbe32s(f, &env->CP0_Random);
92 qemu_put_sbe32s(f, &env->CP0_VPEControl);
93 qemu_put_sbe32s(f, &env->CP0_VPEConf0);
94 qemu_put_sbe32s(f, &env->CP0_VPEConf1);
98 qemu_put_sbe32s(f, &env->CP0_VPEOpt);
102 qemu_put_sbe32s(f, &env->CP0_PageMask);
103 qemu_put_sbe32s(f, &env->CP0_PageGrain);
104 qemu_put_sbe32s(f, &env->CP0_Wired);
105 qemu_put_sbe32s(f, &env->CP0_SRSConf0);
106 qemu_put_sbe32s(f, &env->CP0_SRSConf1);
107 qemu_put_sbe32s(f, &env->CP0_SRSConf2);
108 qemu_put_sbe32s(f, &env->CP0_SRSConf3);
109 qemu_put_sbe32s(f, &env->CP0_SRSConf4);
110 qemu_put_sbe32s(f, &env->CP0_HWREna);
112 qemu_put_sbe32s(f, &env->CP0_Count);
114 qemu_put_sbe32s(f, &env->CP0_Compare);
115 qemu_put_sbe32s(f, &env->CP0_Status);
116 qemu_put_sbe32s(f, &env->CP0_IntCtl);
117 qemu_put_sbe32s(f, &env->CP0_SRSCtl);
118 qemu_put_sbe32s(f, &env->CP0_SRSMap);
119 qemu_put_sbe32s(f, &env->CP0_Cause);
121 qemu_put_sbe32s(f, &env->CP0_PRid);
122 qemu_put_sbe32s(f, &env->CP0_EBase);
123 qemu_put_sbe32s(f, &env->CP0_Config0);
124 qemu_put_sbe32s(f, &env->CP0_Config1);
125 qemu_put_sbe32s(f, &env->CP0_Config2);
126 qemu_put_sbe32s(f, &env->CP0_Config3);
127 qemu_put_sbe32s(f, &env->CP0_Config6);
128 qemu_put_sbe32s(f, &env->CP0_Config7);
133 qemu_put_sbe32s(f, &env->CP0_WatchHi[i]);
135 qemu_put_sbe32s(f, &env->CP0_Framemask);
136 qemu_put_sbe32s(f, &env->CP0_Debug);
138 qemu_put_sbe32s(f, &env->CP0_Performance0);
139 qemu_put_sbe32s(f, &env->CP0_TagLo);
140 qemu_put_sbe32s(f, &env->CP0_DataLo);
141 qemu_put_sbe32s(f, &env->CP0_TagHi);
142 qemu_put_sbe32s(f, &env->CP0_DataHi);
144 qemu_put_sbe32s(f, &env->CP0_DESAVE);
