Lines Matching refs:cpu_env
429 static TCGv_ptr cpu_env;
557 tcg_gen_ld_i32(t2, cpu_env, offsetof(CPUState, CP0_SRSCtl));
562 tcg_gen_add_ptr(addr, cpu_env, addr);
580 tcg_gen_ld_i32(t2, cpu_env, offsetof(CPUState, CP0_SRSCtl));
585 tcg_gen_add_ptr(addr, cpu_env, addr);
597 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[FP_ENDIAN_IDX]));
602 tcg_gen_st_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[FP_ENDIAN_IDX]));
607 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[!FP_ENDIAN_IDX]));
612 tcg_gen_st_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[!FP_ENDIAN_IDX]));
618 tcg_gen_ld_i64(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].d));
633 tcg_gen_st_i64(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].d));
922 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, lladdr)); \
923 tcg_gen_st_tl(ret, cpu_env, offsetof(CPUState, llval)); \
949 tcg_gen_st_tl(arg2, cpu_env, offsetof(CPUState, CP0_BadVAddr)); \
952 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, lladdr)); \
955 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, llreg)); \
956 tcg_gen_st_tl(arg1, cpu_env, offsetof(CPUState, llnewval)); \
2872 tcg_gen_ld_i32(t0, cpu_env, off);
2879 tcg_gen_ld_tl(arg, cpu_env, off);
2888 tcg_gen_st_i32(t0, cpu_env, off);
2895 tcg_gen_st_tl(arg, cpu_env, off);
2979 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryLo0));
3025 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryLo1));
3036 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_Context));
3112 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_BadVAddr));
3141 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryHi));
3198 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EPC));
3288 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_XContext));
3342 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_DEPC));
3445 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_ErrorEPC));
4127 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_YQMask));
4132 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_VPESchedule));
4137 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_VPEScheFBack));
4152 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryLo0));
4197 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryLo1));
4207 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_Context));
4282 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_BadVAddr));
4310 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryHi));
4366 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EPC));
4453 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_XContext));
4505 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_DEPC));
4608 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_ErrorEPC));
4701 tcg_gen_st_tl(arg, cpu_env, offsetof(CPUState, CP0_VPESchedule));
4706 tcg_gen_st_tl(arg, cpu_env, offsetof(CPUState, CP0_VPEScheFBack));
4937 tcg_gen_st_tl(arg, cpu_env, offsetof(CPUState, CP0_EPC));
5084 tcg_gen_st_tl(arg, cpu_env, offsetof(CPUState, CP0_DEPC));
5187 tcg_gen_st_tl(arg, cpu_env, offsetof(CPUState, CP0_ErrorEPC));
7876 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, tls_value));
8538 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
