Lines Matching refs:vHi
1527 HReg vHi, vLo, vec;
1528 iselDVecExpr(&vHi, &vLo, env, e->Iex.Unop.arg);
1536 case Iop_V256to64_2: vec = vHi; off = -16; break;
1537 case Iop_V256to64_3: vec = vHi; off = -8; break;
3008 HReg vHi, vLo;
3009 iselDVecExpr(&vHi, &vLo, env, e->Iex.Unop.arg);
3010 return (e->Iex.Unop.op == Iop_V256toV128_1) ? vHi : vLo;
3420 HReg vHi = newVRegV(env);
3426 addInstr(env, AMD64Instr_SseLdSt(True/*load*/, 16, vHi, am16));
3427 *rHi = vHi;
3433 HReg vHi = newVRegV(env);
3439 addInstr(env, AMD64Instr_SseLdSt(True/*load*/, 16, vHi, am16));
3440 *rHi = vHi;
3449 HReg vHi = generate_zeroes_V128(env);
3451 addInstr(env, mk_vMOVsd_RR(vHi, vLo));
3452 *rHi = vHi;
3631 HReg vHi = newVRegV(env);
3644 addInstr(env, AMD64Instr_SseLdSt(True/*load*/, 16, vHi, m16_rsp));
3649 *rHi = vHi;
3721 HReg vHi, vLo;
3722 iselDVecExpr(&vHi, &vLo, env, stmt->Ist.Store.data);
3724 addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 16, vHi, am16));
3777 HReg vHi, vLo;
3778 iselDVecExpr(&vHi, &vLo, env, stmt->Ist.Put.data);
3783 addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 16, vHi, am16));
