Lines Matching refs:X0100
2693 #define X0100 BITS4(0,1,0,0)
2953 case ARMalu_ADD: subopc = X0100; break;
3422 case ARMvfp_MUL: pqrs = X0100; break;
3447 case ARMvfp_MUL: pqrs = X0100; break;
3468 insn = XXXXXXXX(0xE, X1110,X1011,X0000,dD,X1011,X0100,dM);
3474 insn = XXXXXXXX(0xE, X1110,X1011,X0001,dD,X1011,X0100,dM);
3519 UInt insn = XXXXXXXX(0xE, X1110, X1011, X0100, dD, X1011, X0100, dM);
3529 UInt insn = XXXXXXXX(cc, X1110,X1011,X0000,dD,X1011,X0100,dM);
3624 X1011, X0100, regD);
3634 X1011, X0100, regD);
3683 insn = XXXXXXXX(0xF, X0100, BITS4(0, D, bL, 0),
3703 insn = XXXXXXXX(0xF, X0100, BITS4(0, D, bL, 0),
3941 regD, X0100, BITS4(1,Q,M,0), regM);
3945 regD, X0100, BITS4(0,Q,M,0), regM);
4053 insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X1011, regD, X0100,
4069 insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X1011, regD, X0100,
4366 X0100, BITS4(N,Q,M,0), regM);
4370 X0100, BITS4(N,Q,M,0), regM);
4374 X0100, BITS4(N,Q,M,1), regM);
4378 X0100, BITS4(N,Q,M,1), regM);
4713 #undef X0100
