Lines Matching refs:Min
1113 i->Min.LI.dst = dst;
1114 i->Min.LI.imm = imm;
1122 i->Min.Alu.op = op;
1123 i->Min.Alu.dst = dst;
1124 i->Min.Alu.srcL = srcL;
1125 i->Min.Alu.srcR = srcR;
1134 i->Min.Shft.op = op;
1135 i->Min.Shft.sz32 = sz32;
1136 i->Min.Shft.dst = dst;
1137 i->Min.Shft.srcL = srcL;
1138 i->Min.Shft.srcR = srcR;
1146 i->Min.Unary.op = op;
1147 i->Min.Unary.dst = dst;
1148 i->Min.Unary.src = src;
1157 i->Min.Cmp.syned = syned;
1158 i->Min.Cmp.sz32 = sz32;
1159 i->Min.Cmp.dst = dst;
1160 i->Min.Cmp.srcL = srcL;
1161 i->Min.Cmp.srcR = srcR;
1162 i->Min.Cmp.cond = cond;
1172 i->Min.Mul.syned = syned;
1173 i->Min.Mul.widening = wid; /* widen=True else False */
1174 i->Min.Mul.sz32 = sz32; /* True = 32 bits */
1175 i->Min.Mul.dst = dst;
1176 i->Min.Mul.srcL = srcL;
1177 i->Min.Mul.srcR = srcR;
1187 i->Min.Macc.op = Macc_SUB;
1188 i->Min.Macc.syned = syned;
1189 i->Min.Macc.srcL = srcL;
1190 i->Min.Macc.srcR = srcR;
1200 i->Min.Macc.op = Macc_ADD;
1201 i->Min.Macc.syned = syned;
1202 i->Min.Macc.srcL = srcL;
1203 i->Min.Macc.srcR = srcR;
1212 i->Min.Div.syned = syned;
1213 i->Min.Div.sz32 = sz32; /* True = 32 bits */
1214 i->Min.Div.srcL = srcL;
1215 i->Min.Div.srcR = srcR;
1225 i->Min.Call.cond = cond;
1226 i->Min.Call.target = target;
1227 i->Min.Call.argiregs = argiregs;
1228 i->Min.Call.src = src;
1240 i->Min.Call.cond = cond;
1241 i->Min.Call.target = target;
1242 i->Min.Call.argiregs = argiregs;
1253 i->Min.XDirect.dstGA = dstGA;
1254 i->Min.XDirect.amPC = amPC;
1255 i->Min.XDirect.cond = cond;
1256 i->Min.XDirect.toFastEP = toFastEP;
1264 i->Min.XIndir.dstGA = dstGA;
1265 i->Min.XIndir.amPC = amPC;
1266 i->Min.XIndir.cond = cond;
1274 i->Min.XAssisted.dstGA = dstGA;
1275 i->Min.XAssisted.amPC = amPC;
1276 i->Min.XAssisted.cond = cond;
1277 i->Min.XAssisted.jk = jk;
1285 i->Min.Load.sz = sz;
1286 i->Min.Load.src = src;
1287 i->Min.Load.dst = dst;
1299 i->Min.Store.sz = sz;
1300 i->Min.Store.src = src;
1301 i->Min.Store.dst = dst;
1313 i->Min.LoadL.sz = sz;
1314 i->Min.LoadL.src = src;
1315 i->Min.LoadL.dst = dst;
1327 i->Min.StoreC.sz = sz;
1328 i->Min.StoreC.src = src;
1329 i->Min.StoreC.dst = dst;
1341 i->Min.MtHL.src = src;
1349 i->Min.MtHL.src = src;
1357 i->Min.MfHL.dst = dst;
1365 i->Min.MfHL.dst = dst;
1374 i->Min.RdWrLR.wrLR = wrLR;
1375 i->Min.RdWrLR.gpr = gpr;
1383 i->Min.FpLdSt.isLoad = isLoad;
1384 i->Min.FpLdSt.sz = sz;
1385 i->Min.FpLdSt.reg = reg;
1386 i->Min.FpLdSt.addr = addr;
1395 i->Min.FpUnary.op = op;
1396 i->Min.FpUnary.dst = dst;
1397 i->Min.FpUnary.src = src;
1405 i->Min.FpBinary.op = op;
1406 i->Min.FpBinary.dst = dst;
1407 i->Min.FpBinary.srcL = srcL;
1408 i->Min.FpBinary.srcR = srcR;
1416 i->Min.FpConvert.op = op;
1417 i->Min.FpConvert.dst = dst;
1418 i->Min.FpConvert.src = src;
1428 i->Min.FpCompare.op = op;
1429 i->Min.FpCompare.dst = dst;
1430 i->Min.FpCompare.srcL = srcL;
1431 i->Min.FpCompare.srcR = srcR;
1432 i->Min.FpCompare.cond1 = cond1;
1441 i->Min.MovCond.dst = dst;
1442 i->Min.MovCond.srcL = argL;
1443 i->Min.MovCond.srcR = argR;
1444 i->Min.MovCond.condR = condR;
1445 i->Min.MovCond.cond = cond;
1453 i->Min.MtFCSR.src = src;
1461 i->Min.MfFCSR.dst = dst;
1469 i->Min.EvCheck.amCounter = amCounter;
1470 i->Min.EvCheck.amFailAddr = amFailAddr;
1492 ppLoadImm(i->Min.LI.dst, i->Min
1495 HReg r_srcL = i->Min.Alu.srcL;
1496 MIPSRH *rh_srcR = i->Min.Alu.srcR;
1498 vex_printf("%s ", showMIPSAluOp(i->Min.Alu.op,
1500 ppHRegMIPS(i->Min.Alu.dst, mode64);
1508 HReg r_srcL = i->Min.Shft.srcL;
1509 MIPSRH *rh_srcR = i->Min.Shft.srcR;
1510 vex_printf("%s ", showMIPSShftOp(i->Min.Shft.op,
1512 i->Min.Shft.sz32));
1513 ppHRegMIPS(i->Min.Shft.dst, mode64);
1521 vex_printf("%s ", showMIPSUnaryOp(i->Min.Unary.op));
1522 ppHRegMIPS(i->Min.Unary.dst, mode64);
1524 ppHRegMIPS(i->Min.Unary.src, mode64);
1529 ppHRegMIPS(i->Min.Cmp.dst, mode64);
1530 vex_printf(" = %s ( ", showMIPSCondCode(i->Min.Cmp.cond));
1531 ppHRegMIPS(i->Min.Cmp.srcL, mode64);
1533 ppHRegMIPS(i->Min.Cmp.srcR, mode64);
1539 switch (i->Min.Mul.widening) {
1542 ppHRegMIPS(i->Min.Mul.dst, mode64);
1544 ppHRegMIPS(i->Min.Mul.srcL, mode64);
1546 ppHRegMIPS(i->Min.Mul.srcR, mode64);
1549 vex_printf("%s%s ", i->Min.Mul.sz32 ? "mult" : "dmult",
1550 i->Min.Mul.syned ? "" : "u");
1551 ppHRegMIPS(i->Min.Mul.dst, mode64);
1553 ppHRegMIPS(i->Min.Mul.srcL, mode64);
1555 ppHRegMIPS(i->Min.Mul.srcR, mode64);
1562 ppHRegMIPS(i->Min.MtHL.src, mode64);
1567 ppHRegMIPS(i->Min.MtHL.src, mode64);
1572 ppHRegMIPS(i->Min.MfHL.dst, mode64);
1577 ppHRegMIPS(i->Min.MfHL.dst, mode64);
1581 vex_printf("%s ", showMIPSMaccOp(i->Min.Macc.op, i->Min.Macc.syned));
1582 ppHRegMIPS(i->Min.Macc.srcL, mode64);
1584 ppHRegMIPS(i->Min.Macc.srcR, mode64);
1588 if (!i->Min.Div.sz32)
1591 vex_printf("%s ", i->Min.Div.syned ? "s" : "u");
1592 ppHRegMIPS(i->Min.Div.srcL, mode64);
1594 ppHRegMIPS(i->Min.Div.srcR, mode64);
1600 if (i->Min.Call.cond != MIPScc_AL) {
1601 vex_printf("if (%s) ", showMIPSCondCode(i->Min.Call.cond));
1604 ppLoadImm(hregMIPS_GPR11(mode64), i->Min.Call.target, mode64);
1608 if (i->Min.Call.argiregs & (1 << n)) {
1610 if ((i->Min.Call.argiregs >> n) > 1)
1620 showMIPSCondCode(i->Min.XDirect.cond));
1621 vex_printf("move $9, 0x%x,", i->Min.XDirect.dstGA);
1623 ppMIPSAMode(i->Min.XDirect.amPC, mode64);
1625 i->Min.XDirect.toFastEP ? "fast" : "slow");
1630 showMIPSCondCode(i->Min.XIndir.cond));
1631 ppHRegMIPS(i->Min.XIndir.dstGA, mode64);
1633 ppMIPSAMode(i->Min.XIndir.amPC, mode64);
1639 showMIPSCondCode(i->Min.XAssisted.cond));
1641 ppHRegMIPS(i->Min.XAssisted.dstGA, mode64);
1643 ppMIPSAMode(i->Min.XAssisted.amPC, mode64);
1645 (Int)i->Min.XAssisted.jk);
1649 Bool idxd = toBool(i->Min.Load.src->tag == Mam_RR);
1650 UChar sz = i->Min.Load.sz;
1653 ppHRegMIPS(i->Min.Load.dst, mode64);
1655 ppMIPSAMode(i->Min.Load.src, mode64);
1659 UChar sz = i->Min.Store.sz;
1660 Bool idxd = toBool(i->Min.Store.dst->tag == Mam_RR);
1663 ppHRegMIPS(i->Min.Store.src, mode64);
1665 ppMIPSAMode(i->Min.Store.dst, mode64);
1670 ppHRegMIPS(i->Min.LoadL.dst, mode64);
1672 ppMIPSAMode(i->Min.LoadL.src, mode64);
1677 ppHRegMIPS(i->Min.StoreC.src, mode64);
1679 ppMIPSAMode(i->Min.StoreC.dst, mode64);
1683 vex_printf("%s ", i->Min.RdWrLR.wrLR ? "mtlr" : "mflr");
1684 ppHRegMIPS(i->Min.RdWrLR.gpr, mode64);
1688 vex_printf("%s ", showMIPSFpOp(i->Min.FpUnary.op));
1689 ppHRegMIPS(i->Min.FpUnary.dst, mode64);
1691 ppHRegMIPS(i->Min.FpUnary.src, mode64);
1694 vex_printf("%s", showMIPSFpOp(i->Min.FpBinary.op));
1695 ppHRegMIPS(i->Min.FpBinary.dst, mode64);
1697 ppHRegMIPS(i->Min.FpBinary.srcL, mode64);
1699 ppHRegMIPS(i->Min.FpBinary.srcR, mode64);
1702 vex_printf("%s", showMIPSFpOp(i->Min.FpConvert.op));
1703 ppHRegMIPS(i->Min.FpConvert.dst, mode64);
1705 ppHRegMIPS(i->Min.FpConvert.src, mode64);
1708 vex_printf("%s ", showMIPSFpOp(i->Min.FpCompare.op));
1709 ppHRegMIPS(i->Min.FpCompare.srcL, mode64);
1711 ppHRegMIPS(i->Min.FpCompare.srcR, mode64);
1712 vex_printf(" cond: %c", i->Min.FpCompare.cond1);
1715 vex_printf("%s ", showMIPSFpOp(i->Min.FpMulAcc.op));
1716 ppHRegMIPS(i->Min.FpMulAcc.dst, mode64);
1718 ppHRegMIPS(i->Min.FpMulAcc.srcML, mode64);
1720 ppHRegMIPS(i->Min.FpMulAcc.srcMR, mode64);
1722 ppHRegMIPS(i->Min.FpMulAcc.srcAcc, mode64);
1725 if (i->Min.FpLdSt.sz == 4) {
1726 if (i->Min.FpLdSt.isLoad) {
1728 ppHRegMIPS(i->Min.FpLdSt.reg, mode64);
1730 ppMIPSAMode(i->Min.FpLdSt.addr, mode64);
1733 ppHRegMIPS(i->Min.FpLdSt.reg, mode64);
1735 ppMIPSAMode(i->Min.FpLdSt.addr, mode64);
1737 } else if (i->Min.FpLdSt.sz == 8) {
1738 if (i->Min.FpLdSt.isLoad) {
1743 ppHRegMIPS(i->Min.FpLdSt.reg, mode64);
1745 ppMIPSAMode(i->Min.FpLdSt.addr, mode64);
1751 ppHRegMIPS(i->Min.FpLdSt.reg, mode64);
1753 ppMIPSAMode(i->Min.FpLdSt.addr, mode64);
1759 if (i->Min.MovCond.cond == MIPScc_MI) {
1768 ppHRegMIPS(i->Min.MtFCSR.src, mode64);
1775 ppHRegMIPS(i->Min.MfFCSR.dst, mode64);
1781 ppMIPSAMode(i->Min.EvCheck.amCounter, mode64);
1784 ppMIPSAMode(i->Min.EvCheck.amCounter, mode64);
1786 ppMIPSAMode(i->Min.EvCheck.amFailAddr, mode64);
1812 addHRegUse(u, HRmWrite, i->Min.LI.dst);
1815 addHRegUse(u, HRmRead, i->Min.Alu.srcL);
1816 addRegUsage_MIPSRH(u, i->Min.Alu.srcR);
1817 addHRegUse(u, HRmWrite, i->Min.Alu.dst);
1820 addHRegUse(u, HRmRead, i->Min.Shft.srcL);
1821 addRegUsage_MIPSRH(u, i->Min.Shft.srcR);
1822 addHRegUse(u, HRmWrite, i->Min.Shft.dst);
1825 addHRegUse(u, HRmRead, i->Min.Cmp.srcL);
1826 addHRegUse(u, HRmRead, i->Min.Cmp.srcR);
1827 addHRegUse(u, HRmWrite, i->Min.Cmp.dst);
1830 addHRegUse(u, HRmRead, i->Min.Unary.src);
1831 addHRegUse(u, HRmWrite, i->Min.Unary.dst);
1834 addHRegUse(u, HRmWrite, i->Min.Mul.dst);
1835 addHRegUse(u, HRmRead, i->Min.Mul.srcL);
1836 addHRegUse(u, HRmRead, i->Min.Mul.srcR);
1842 addHRegUse(u, HRmRead, i->Min.MtHL.src);
1848 addHRegUse(u, HRmWrite, i->Min.MfHL.dst);
1851 addHRegUse(u, HRmRead, i->Min.MtFCSR.src);
1854 addHRegUse(u, HRmWrite, i->Min.MfFCSR.dst);
1859 addHRegUse(u, HRmRead, i->Min.Macc.srcL);
1860 addHRegUse(u, HRmRead, i->Min.Macc.srcR);
1865 addHRegUse(u, HRmRead, i->Min.Div.srcL);
1866 addHRegUse(u, HRmRead, i->Min.Div.srcR);
1869 if (i->Min.Call.cond != MIPScc_AL)
1870 addHRegUse(u, HRmRead, i->Min.Call.src);
1898 argir = i->Min.Call.argiregs;
1917 addRegUsage_MIPSAMode(u, i->Min.XDirect.amPC);
1920 addHRegUse(u, HRmRead, i->Min.XIndir.dstGA);
1921 addRegUsage_MIPSAMode(u, i->Min.XIndir.amPC);
1924 addHRegUse(u, HRmRead, i->Min.XAssisted.dstGA);
1925 addRegUsage_MIPSAMode(u, i->Min.XAssisted.amPC);
1928 addRegUsage_MIPSAMode(u, i->Min.Load.src);
1929 addHRegUse(u, HRmWrite, i->Min.Load.dst);
1932 addHRegUse(u, HRmRead, i->Min.Store.src);
1933 addRegUsage_MIPSAMode(u, i->Min.Store.dst);
1936 addRegUsage_MIPSAMode(u, i->Min.LoadL.src);
1937 addHRegUse(u, HRmWrite, i->Min.LoadL.dst);
1940 addHRegUse(u, HRmWrite, i->Min.StoreC.src);
1941 addHRegUse(u, HRmRead, i->Min.StoreC.src);
1942 addRegUsage_MIPSAMode(u, i->Min.StoreC.dst);
1945 addHRegUse(u, (i->Min.RdWrLR.wrLR ? HRmRead : HRmWrite),
1946 i->Min.RdWrLR.gpr);
1949 if (i->Min.FpLdSt.sz == 4) {
1950 addHRegUse(u, (i->Min.FpLdSt.isLoad ? HRmWrite : HRmRead),
1951 i->Min.FpLdSt.reg);
1952 addRegUsage_MIPSAMode(u, i->Min.FpLdSt.addr);
1954 } else if (i->Min.FpLdSt.sz == 8) {
1956 addHRegUse(u, (i->Min.FpLdSt.isLoad ? HRmWrite : HRmRead),
1957 i->Min.FpLdSt.reg);
1958 addRegUsage_MIPSAMode(u, i->Min.FpLdSt.addr);
1960 addHRegUse(u, (i->Min.FpLdSt.isLoad ? HRmWrite : HRmRead),
1961 i->Min.FpLdSt.reg);
1962 addRegUsage_MIPSAMode(u, i->Min.FpLdSt.addr);
1963 addRegUsage_MIPSAMode(u, nextMIPSAModeFloat(i->Min.FpLdSt.addr));
1969 if (i->Min.FpUnary.op == Mfp_CVTD) {
1970 addHRegUse(u, HRmWrite, i->Min.FpUnary.dst);
1971 addHRegUse(u, HRmRead, i->Min.FpUnary.src);
1974 addHRegUse(u, HRmWrite, i->Min.FpUnary.dst);
1975 addHRegUse(u, HRmRead, i->Min.FpUnary.src);
1979 addHRegUse(u, HRmWrite, i->Min.FpBinary.dst);
1980 addHRegUse(u, HRmRead, i->Min.FpBinary.srcL);
1981 addHRegUse(u, HRmRead, i->Min.FpBinary.srcR);
1984 addHRegUse(u, HRmWrite, i->Min.FpConvert.dst);
1985 addHRegUse(u, HRmRead, i->Min.FpConvert.src);
1988 addHRegUse(u, HRmWrite, i->Min.FpCompare.dst);
1989 addHRegUse(u, HRmRead, i->Min.FpCompare.srcL);
1990 addHRegUse(u, HRmRead, i->Min.FpCompare.srcR);
1993 if (i->Min.MovCond.srcR->tag == Mrh_Reg) {
1994 addHRegUse(u, HRmRead, i->Min.MovCond.srcR->Mrh.Reg.reg);
1996 addHRegUse(u, HRmRead, i->Min.MovCond.srcL);
1997 addHRegUse(u, HRmRead, i->Min.MovCond.condR);
1998 addHRegUse(u, HRmWrite, i->Min.MovCond.dst);
2003 addRegUsage_MIPSAMode(u, i->Min.EvCheck.amCounter);
2004 addRegUsage_MIPSAMode(u, i->Min.EvCheck.amFailAddr);
2026 mapReg(m, &i->Min.LI.dst);
2029 mapReg(m, &i->Min.Alu.srcL);
2030 mapRegs_MIPSRH(m, i->Min.Alu.srcR);
2031 mapReg(m, &i->Min.Alu.dst);
2034 mapReg(m, &i->Min.Shft.srcL);
2035 mapRegs_MIPSRH(m, i->Min.Shft.srcR);
2036 mapReg(m, &i->Min.Shft.dst);
2039 mapReg(m, &i->Min.Cmp.srcL);
2040 mapReg(m, &i->Min.Cmp.srcR);
2041 mapReg(m, &i->Min.Cmp.dst);
2044 mapReg(m, &i->Min.Unary.src);
2045 mapReg(m, &i->Min.Unary.dst);
2048 mapReg(m, &i->Min.Mul.dst);
2049 mapReg(m, &i->Min.Mul.srcL);
2050 mapReg(m, &i->Min.Mul.srcR);
2054 mapReg(m, &i->Min.MtHL.src);
2058 mapReg(m, &i->Min.MfHL.dst);
2061 mapReg(m, &i->Min.Macc.srcL);
2062 mapReg(m, &i->Min.Macc.srcR);
2065 mapReg(m, &i->Min.Div.srcL);
2066 mapReg(m, &i->Min.Div.srcR);
2070 if (i->Min.Call.cond != MIPScc_AL)
2071 mapReg(m, &i->Min.Call.src);
2075 mapRegs_MIPSAMode(m, i->Min.XDirect.amPC);
2078 mapReg(m, &i->Min.XIndir.dstGA);
2079 mapRegs_MIPSAMode(m, i->Min.XIndir.amPC);
2082 mapReg(m, &i->Min.XAssisted.dstGA);
2083 mapRegs_MIPSAMode(m, i->Min.XAssisted.amPC);
2086 mapRegs_MIPSAMode(m, i->Min.Load.src);
2087 mapReg(m, &i->Min.Load.dst);
2090 mapReg(m, &i->Min.Store.src);
2091 mapRegs_MIPSAMode(m, i->Min.Store.dst);
2094 mapRegs_MIPSAMode(m, i->Min.LoadL.src);
2095 mapReg(m, &i->Min.LoadL.dst);
2098 mapReg(m, &i->Min.StoreC.src);
2099 mapRegs_MIPSAMode(m, i->Min.StoreC.dst);
2102 mapReg(m, &i->Min.RdWrLR.gpr);
2105 if (i->Min.FpLdSt.sz == 4) {
2106 mapReg(m, &i->Min.FpLdSt.reg);
2107 mapRegs_MIPSAMode(m, i->Min.FpLdSt.addr);
2109 } else if (i->Min.FpLdSt.sz == 8) {
2111 mapReg(m, &i->Min.FpLdSt.reg);
2112 mapRegs_MIPSAMode(m, i->Min.FpLdSt.addr);
2114 mapReg(m, &i->Min.FpLdSt.reg);
2115 mapRegs_MIPSAMode(m, i->Min.FpLdSt.addr);
2116 mapRegs_MIPSAMode(m, nextMIPSAModeFloat(i->Min.FpLdSt.addr));
2122 if (i->Min.FpUnary.op == Mfp_CVTD) {
2123 mapReg(m, &i->Min.FpUnary.dst);
2124 mapReg(m, &i->Min.FpUnary.src);
2127 mapReg(m, &i->Min.FpUnary.dst);
2128 mapReg(m, &i->Min.FpUnary.src);
2132 mapReg(m, &i->Min.FpBinary.dst);
2133 mapReg(m, &i->Min.FpBinary.srcL);
2134 mapReg(m, &i->Min.FpBinary.srcR);
2137 mapReg(m, &i->Min.FpConvert.dst);
2138 mapReg(m, &i->Min.FpConvert.src);
2141 mapReg(m, &i->Min.FpCompare.dst);
2142 mapReg(m, &i->Min.FpCompare.srcL);
2143 mapReg(m, &i->Min.FpCompare.srcR);
2146 mapReg(m, &i->Min.MtFCSR.src);
2149 mapReg(m, &i->Min.MfFCSR.dst);
2152 if (i->Min.MovCond.srcR->tag == Mrh_Reg) {
2153 mapReg(m, &(i->Min.MovCond.srcR->Mrh.Reg.reg));
2155 mapReg(m, &i->Min.MovCond.srcL);
2156 mapReg(m, &i->Min.MovCond.condR);
2157 mapReg(m, &i->Min.MovCond.dst);
2163 mapRegs_MIPSAMode(m, i->Min.EvCheck.amCounter);
2164 mapRegs_MIPSAMode(m, i->Min.EvCheck.amFailAddr);
2186 if (i->Min.Alu.op != Malu_OR)
2188 if (i->Min.Alu.srcR->tag != Mrh_Reg)
2190 if (i->Min.Alu.srcR->Mrh.Reg.reg != i->Min.Alu.srcL)
2192 *src = i->Min.Alu.srcL;
2193 *dst = i->Min.Alu.dst;
2709 MIPSRH *srcR = i->Min.MovCond.srcR;
2710 UInt condR = iregNo(i->Min.MovCond.condR, mode64);
2711 UInt dst = iregNo(i->Min.MovCond.dst, mode64);
2713 UInt srcL = iregNo(i->Min.MovCond.srcL, mode64);
2716 if (i->Min.MovCond.cond == MIPScc_MI) {
2734 p = mkLoadImm(p, iregNo(i->Min.LI.dst, mode64), i->Min.LI.imm, mode64);
2738 MIPSRH *srcR = i->Min.Alu.srcR;
2740 UInt r_dst = iregNo(i->Min.Alu.dst, mode64);
2741 UInt r_srcL = iregNo(i->Min.Alu.srcL, mode64);
2744 switch (i->Min.Alu.op) {
2827 MIPSRH *srcR = i->Min.Shft.srcR;
2828 Bool sz32 = i->Min.Shft.sz32;
2830 UInt r_dst = iregNo(i->Min.Shft.dst, mode64);
2831 UInt r_srcL = iregNo(i->Min.Shft.srcL, mode64);
2836 switch (i->Min.Shft.op) {
2924 UInt r_dst = iregNo(i->Min.Unary.dst, mode64);
2925 UInt r_src = iregNo(i->Min.Unary.src, mode64);
2927 switch (i->Min.Unary.op) {
2943 UInt r_srcL = iregNo(i->Min.Cmp.srcL, mode64);
2944 UInt r_srcR = iregNo(i->Min.Cmp.srcR, mode64);
2945 UInt r_dst = iregNo(i->Min.Cmp.dst, mode64);
2947 switch (i->Min.Cmp.cond) {
3005 Bool syned = i->Min.Mul.syned;
3006 Bool widening = i->Min.Mul.widening;
3007 Bool sz32 = i->Min.Mul.sz32;
3008 UInt r_srcL = iregNo(i->Min.Mul.srcL, mode64);
3009 UInt r_srcR = iregNo(i->Min.Mul.srcR, mode64);
3010 UInt r_dst = iregNo(i->Min.Mul.dst, mode64);
3039 Bool syned = i->Min.Macc.syned;
3040 UInt r_srcL = iregNo(i->Min.Macc.srcL, mode64);
3041 UInt r_srcR = iregNo(i->Min.Macc.srcR, mode64);
3044 switch (i->Min.Macc.op) {
3058 switch (i->Min.Macc.op) {
3078 Bool syned = i->Min.Div.syned;
3079 Bool sz32 = i->Min.Div.sz32;
3080 UInt r_srcL = iregNo(i->Min.Div.srcL, mode64);
3081 UInt r_srcR = iregNo(i->Min.Div.srcR, mode64);
3102 UInt r_src = iregNo(i->Min.MtHL.src, mode64);
3108 UInt r_src = iregNo(i->Min.MtHL.src, mode64);
3114 UInt r_dst = iregNo(i->Min.MfHL.dst, mode64);
3120 UInt r_dst = iregNo(i->Min.MfHL.dst, mode64);
3126 UInt r_src = iregNo(i->Min.MtFCSR.src, mode64);
3133 UInt r_dst = iregNo(i->Min.MfFCSR.dst, mode64);
3140 MIPSCondCode cond = i->Min.Call.cond;
3154 p = mkLoadImm(p, r_dst, i->Min.Call.target, mode64);
3162 UInt r_src = iregNo(i->Min.Call.src, mode64);
3190 if (i->Min.XDirect.cond != MIPScc_AL) {
3191 vassert(i->Min.XDirect.cond != MIPScc_NV);
3200 (ULong)i->Min.XDirect.dstGA, mode64);
3202 /*r*/9, i->Min.XDirect.amPC, mode64);
3212 = i->Min.XDirect.toFastEP ? disp_cp_chain_me_to_fastEP
3223 if (i->Min.XDirect.cond != MIPScc_AL) {
3251 if (i->Min.XIndir.cond != MIPScc_AL) {
3252 vassert(i->Min.XIndir.cond != MIPScc_NV);
3260 iregNo(i->Min.XIndir.dstGA, mode64),
3261 i->Min.XIndir.amPC, mode64);
3272 if (i->Min.XIndir.cond != MIPScc_AL) {
3291 if (i->Min.XAssisted.cond != MIPScc_AL) {
3292 vassert(i->Min.XAssisted.cond != MIPScc_NV);
3300 iregNo(i->Min.XIndir.dstGA, mode64),
3301 i->Min.XIndir.amPC, mode64);
3305 switch (i->Min.XAssisted.jk) {
3325 ppIRJumpKind(i->Min.XAssisted.jk);
3340 if (i->Min.XAssisted.cond != MIPScc_AL) {
3355 MIPSAMode *am_addr = i->Min.Load.src;
3357 UInt r_dst = iregNo(i->Min.Load.dst, mode64);
3358 UInt opc, sz = i->Min.Load.sz;
3384 UInt r_dst = iregNo(i->Min.Load.dst, mode64);
3385 UInt opc, sz = i->Min.Load.sz;
3412 MIPSAMode *am_addr = i->Min.Store.dst;
3414 UInt r_src = iregNo(i->Min.Store.src, mode64);
3415 UInt opc, sz = i->Min.Store.sz;
3441 UInt r_src = iregNo(i->Min.Store.src, mode64);
3442 UInt opc, sz = i->Min.Store.sz;
3468 MIPSAMode *am_addr = i->Min.LoadL.src;
3471 UInt r_dst = iregNo(i->Min.LoadL.dst, mode64);
3477 MIPSAMode *am_addr = i->Min.StoreC.dst;
3478 UInt r_src = iregNo(i->Min.StoreC.src, mode64);
3486 UInt reg = iregNo(i->Min.RdWrLR.gpr, mode64);
3487 Bool wrLR = i->Min.RdWrLR.wrLR;
3498 MIPSAMode *am_addr = i->Min.FpLdSt.addr;
3499 UChar sz = i->Min.FpLdSt.sz;
3502 UInt f_reg = fregNo(i->Min.FpLdSt.reg, mode64);
3503 if (i->Min.FpLdSt.isLoad) {
3515 UInt f_reg = dregNo(i->Min.FpLdSt.reg);
3516 if (i->Min.FpLdSt.isLoad) {
3558 switch (i->Min.FpUnary.op) {
3560 UInt fr_dst = fregNo(i->Min.FpUnary.dst, mode64);
3561 UInt fr_src = fregNo(i->Min.FpUnary.src, mode64);
3566 UInt fr_dst = dregNo(i->Min.FpUnary.dst);
3567 UInt fr_src = dregNo(i->Min.FpUnary.src);
3572 UInt fr_dst = fregNo(i->Min.FpUnary.dst, mode64);
3573 UInt fr_src = fregNo(i->Min.FpUnary.src, mode64);
3578 UInt fr_dst = dregNo(i->Min.FpUnary.dst);
3579 UInt fr_src = dregNo(i->Min.FpUnary.src);
3584 UInt fr_dst = fregNo(i->Min.FpUnary.dst, mode64);
3585 UInt fr_src = fregNo(i->Min.FpUnary.src, mode64);
3590 UInt fr_dst = dregNo(i->Min.FpUnary.dst);
3591 UInt fr_src = dregNo(i->Min.FpUnary.src);
3596 UInt fr_dst = dregNo(i->Min.FpUnary.dst);
3597 UInt fr_src = fregNo(i->Min.FpUnary.src, mode64);
3602 UInt fr_dst = fregNo(i->Min.FpUnary.dst, mode64);
3603 UInt fr_src = fregNo(i->Min.FpUnary.src, mode64);
3608 UInt fr_dst = dregNo(i->Min.FpUnary.dst);
3609 UInt fr_src = dregNo(i->Min.FpUnary.src);
3614 UInt fr_dst = fregNo(i->Min.FpUnary.dst, mode64);
3615 UInt fr_src = fregNo(i->Min.FpUnary.src, mode64);
3620 UInt fr_dst = dregNo(i->Min.FpUnary.dst);
3621 UInt fr_src = dregNo(i->Min.FpUnary.src);
3626 UInt fr_dst = fregNo(i->Min.FpUnary.dst, mode64);
3627 UInt fr_src = fregNo(i->Min.FpUnary.src, mode64);
3632 UInt fr_dst = dregNo(i->Min.FpUnary.dst);
3633 UInt fr_src = dregNo(i->Min.FpUnary.src);
3644 switch (i->Min.FpBinary.op) {
3646 UInt fr_dst = fregNo(i->Min.FpBinary.dst, mode64);
3647 UInt fr_srcL = fregNo(i->Min.FpBinary.srcL, mode64);
3648 UInt fr_srcR = fregNo(i->Min.FpBinary.srcR, mode64);
3653 UInt fr_dst = fregNo(i->Min.FpBinary.dst, mode64);
3654 UInt fr_srcL = fregNo(i->Min.FpBinary.srcL, mode64);
3655 UInt fr_srcR = fregNo(i->Min.FpBinary.srcR, mode64);
3660 UInt fr_dst = fregNo(i->Min.FpBinary.dst, mode64);
3661 UInt fr_srcL = fregNo(i->Min.FpBinary.srcL, mode64);
3662 UInt fr_srcR = fregNo(i->Min.FpBinary.srcR, mode64);
3667 UInt fr_dst = fregNo(i->Min.FpBinary.dst, mode64);
3668 UInt fr_srcL = fregNo(i->Min.FpBinary.srcL, mode64);
3669 UInt fr_srcR = fregNo(i->Min.FpBinary.srcR, mode64);
3674 UInt fr_dst = dregNo(i->Min.FpBinary.dst);
3675 UInt fr_srcL = dregNo(i->Min.FpBinary.srcL);
3676 UInt fr_srcR = dregNo(i->Min.FpBinary.srcR);
3681 UInt fr_dst = dregNo(i->Min.FpBinary.dst);
3682 UInt fr_srcL = dregNo(i->Min.FpBinary.srcL);
3683 UInt fr_srcR = dregNo(i->Min.FpBinary.srcR);
3688 UInt fr_dst = dregNo(i->Min.FpBinary.dst);
3689 UInt fr_srcL = dregNo(i->Min.FpBinary.srcL);
3690 UInt fr_srcR = dregNo(i->Min.FpBinary.srcR);
3695 UInt fr_dst = dregNo(i->Min.FpBinary.dst);
3696 UInt fr_srcL = dregNo(i->Min.FpBinary.srcL);
3697 UInt fr_srcR = dregNo(i->Min.FpBinary.srcR);
3708 switch (i->Min.FpConvert.op) {
3711 fr_dst = fregNo(i->Min.FpConvert.dst, mode64);
3712 fr_src = dregNo(i->Min.FpConvert.src);
3716 fr_dst = fregNo(i->Min.FpConvert.dst, mode64);
3717 fr_src = fregNo(i->Min.FpConvert.src, mode64);
3721 fr_dst = fregNo(i->Min.FpConvert.dst, mode64);
3722 fr_src = dregNo(i->Min.FpConvert.src);
3726 fr_dst = fregNo(i->Min.FpConvert.dst, mode64);
3727 fr_src = fregNo(i->Min.FpConvert.src, mode64);
3731 fr_dst = dregNo(i->Min.FpConvert.dst);
3732 fr_src = fregNo(i->Min.FpConvert.src, mode64);
3736 fr_dst = fregNo(i->Min.FpConvert.dst, mode64);
3737 fr_src = fregNo(i->Min.FpConvert.src, mode64);
3741 fr_dst = fregNo(i->Min.FpConvert.dst, mode64);
3742 fr_src = dregNo(i->Min.FpConvert.src);
3746 fr_dst = fregNo(i->Min.FpConvert.dst, mode64);
3747 fr_src = dregNo(i->Min.FpConvert.src);
3751 fr_dst = dregNo(i->Min.FpConvert.dst);
3752 fr_src = dregNo(i->Min.FpConvert.src);
3756 fr_dst = fregNo(i->Min.FpConvert.dst, mode64);
3757 fr_src = fregNo(i->Min.FpConvert.src, mode64);
3761 fr_dst = fregNo(i->Min.FpConvert.dst, mode64);
3762 fr_src = dregNo(i->Min.FpConvert.src);
3766 fr_dst = dregNo(i->Min.FpConvert.dst);
3767 fr_src = fregNo(i->Min.FpConvert.src, mode64);
3771 fr_dst = dregNo(i->Min.FpConvert.dst);
3772 fr_src = dregNo(i->Min.FpConvert.src);
3776 fr_dst = fregNo(i->Min.FpConvert.dst, mode64);
3777 fr_src = fregNo(i->Min.FpConvert.src, mode64);
3781 fr_dst = fregNo(i->Min.FpConvert.dst, mode64);
3782 fr_src = dregNo(i->Min.FpConvert.src);
3786 fr_dst = fregNo(i->Min.FpConvert.dst, mode64);
3787 fr_src = fregNo(i->Min.FpConvert.src, mode64);
3791 fr_dst = fregNo(i->Min.FpConvert.dst, mode64);
3792 fr_src = dregNo(i->Min.FpConvert.src);
3803 UInt r_dst = iregNo(i->Min.FpCompare.dst, mode64);
3804 UInt fr_srcL = dregNo(i->Min.FpCompare.srcL);
3805 UInt fr_srcR = dregNo(i->Min.FpCompare.srcR);
3807 switch (i->Min.FpConvert.op) {
3810 (i->Min.FpCompare.cond1 + 48));
3833 i->Min.EvCheck.amCounter, mode64);
3838 i->Min.EvCheck.amCounter, mode64);
3843 i->Min.EvCheck.amFailAddr, mode64);
