1 //===-- XCoreISelLowering.cpp - XCore DAG Lowering Implementation ---------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the XCoreTargetLowering class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #define DEBUG_TYPE "xcore-lower" 15 16 #include "XCoreISelLowering.h" 17 #include "XCore.h" 18 #include "XCoreMachineFunctionInfo.h" 19 #include "XCoreSubtarget.h" 20 #include "XCoreTargetMachine.h" 21 #include "XCoreTargetObjectFile.h" 22 #include "llvm/CodeGen/CallingConvLower.h" 23 #include "llvm/CodeGen/MachineFrameInfo.h" 24 #include "llvm/CodeGen/MachineFunction.h" 25 #include "llvm/CodeGen/MachineInstrBuilder.h" 26 #include "llvm/CodeGen/MachineJumpTableInfo.h" 27 #include "llvm/CodeGen/MachineRegisterInfo.h" 28 #include "llvm/CodeGen/SelectionDAGISel.h" 29 #include "llvm/CodeGen/ValueTypes.h" 30 #include "llvm/IR/CallingConv.h" 31 #include "llvm/IR/DerivedTypes.h" 32 #include "llvm/IR/Function.h" 33 #include "llvm/IR/GlobalAlias.h" 34 #include "llvm/IR/GlobalVariable.h" 35 #include "llvm/IR/Intrinsics.h" 36 #include "llvm/Support/Debug.h" 37 #include "llvm/Support/ErrorHandling.h" 38 #include "llvm/Support/raw_ostream.h" 39 #include <algorithm> 40 41 using namespace llvm; 42 43 const char *XCoreTargetLowering:: 44 getTargetNodeName(unsigned Opcode) const 45 { 46 switch (Opcode) 47 { 48 case XCoreISD::BL : return "XCoreISD::BL"; 49 case XCoreISD::PCRelativeWrapper : return "XCoreISD::PCRelativeWrapper"; 50 case XCoreISD::DPRelativeWrapper : return "XCoreISD::DPRelativeWrapper"; 51 case XCoreISD::CPRelativeWrapper : return "XCoreISD::CPRelativeWrapper"; 52 case XCoreISD::STWSP : return "XCoreISD::STWSP"; 53 case XCoreISD::RETSP : return "XCoreISD::RETSP"; 54 case XCoreISD::LADD : return "XCoreISD::LADD"; 55 case XCoreISD::LSUB : return "XCoreISD::LSUB"; 56 case XCoreISD::LMUL : return "XCoreISD::LMUL"; 57 case XCoreISD::MACCU : return "XCoreISD::MACCU"; 58 case XCoreISD::MACCS : return "XCoreISD::MACCS"; 59 case XCoreISD::CRC8 : return "XCoreISD::CRC8"; 60 case XCoreISD::BR_JT : return "XCoreISD::BR_JT"; 61 case XCoreISD::BR_JT32 : return "XCoreISD::BR_JT32"; 62 default : return NULL; 63 } 64 } 65 66 XCoreTargetLowering::XCoreTargetLowering(XCoreTargetMachine &XTM) 67 : TargetLowering(XTM, new XCoreTargetObjectFile()), 68 TM(XTM), 69 Subtarget(*XTM.getSubtargetImpl()) { 70 71 // Set up the register classes. 72 addRegisterClass(MVT::i32, &XCore::GRRegsRegClass); 73 74 // Compute derived properties from the register classes 75 computeRegisterProperties(); 76 77 // Division is expensive 78 setIntDivIsCheap(false); 79 80 setStackPointerRegisterToSaveRestore(XCore::SP); 81 82 setSchedulingPreference(Sched::RegPressure); 83 84 // Use i32 for setcc operations results (slt, sgt, ...). 85 setBooleanContents(ZeroOrOneBooleanContent); 86 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct? 87 88 // XCore does not have the NodeTypes below. 89 setOperationAction(ISD::BR_CC, MVT::i32, Expand); 90 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 91 setOperationAction(ISD::ADDC, MVT::i32, Expand); 92 setOperationAction(ISD::ADDE, MVT::i32, Expand); 93 setOperationAction(ISD::SUBC, MVT::i32, Expand); 94 setOperationAction(ISD::SUBE, MVT::i32, Expand); 95 96 // Stop the combiner recombining select and set_cc 97 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); 98 99 // 64bit 100 setOperationAction(ISD::ADD, MVT::i64, Custom); 101 setOperationAction(ISD::SUB, MVT::i64, Custom); 102 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Custom); 103 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Custom); 104 setOperationAction(ISD::MULHS, MVT::i32, Expand); 105 setOperationAction(ISD::MULHU, MVT::i32, Expand); 106 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 107 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 108 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 109 110 // Bit Manipulation 111 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 112 setOperationAction(ISD::ROTL , MVT::i32, Expand); 113 setOperationAction(ISD::ROTR , MVT::i32, Expand); 114 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand); 115 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand); 116 117 setOperationAction(ISD::TRAP, MVT::Other, Legal); 118 119 // Jump tables. 120 setOperationAction(ISD::BR_JT, MVT::Other, Custom); 121 122 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 123 setOperationAction(ISD::BlockAddress, MVT::i32 , Custom); 124 125 // Conversion of i64 -> double produces constantpool nodes 126 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 127 128 // Loads 129 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); 130 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); 131 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 132 133 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand); 134 setLoadExtAction(ISD::ZEXTLOAD, MVT::i16, Expand); 135 136 // Custom expand misaligned loads / stores. 137 setOperationAction(ISD::LOAD, MVT::i32, Custom); 138 setOperationAction(ISD::STORE, MVT::i32, Custom); 139 140 // Varargs 141 setOperationAction(ISD::VAEND, MVT::Other, Expand); 142 setOperationAction(ISD::VACOPY, MVT::Other, Expand); 143 setOperationAction(ISD::VAARG, MVT::Other, Custom); 144 setOperationAction(ISD::VASTART, MVT::Other, Custom); 145 146 // Dynamic stack 147 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 148 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 149 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); 150 151 // TRAMPOLINE is custom lowered. 152 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom); 153 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom); 154 155 // We want to custom lower some of our intrinsics. 156 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 157 158 MaxStoresPerMemset = MaxStoresPerMemsetOptSize = 4; 159 MaxStoresPerMemmove = MaxStoresPerMemmoveOptSize 160 = MaxStoresPerMemcpy = MaxStoresPerMemcpyOptSize = 2; 161 162 // We have target-specific dag combine patterns for the following nodes: 163 setTargetDAGCombine(ISD::STORE); 164 setTargetDAGCombine(ISD::ADD); 165 166 setMinFunctionAlignment(1); 167 } 168 169 SDValue XCoreTargetLowering:: 170 LowerOperation(SDValue Op, SelectionDAG &DAG) const { 171 switch (Op.getOpcode()) 172 { 173 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 174 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 175 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 176 case ISD::BR_JT: return LowerBR_JT(Op, DAG); 177 case ISD::LOAD: return LowerLOAD(Op, DAG); 178 case ISD::STORE: return LowerSTORE(Op, DAG); 179 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 180 case ISD::VAARG: return LowerVAARG(Op, DAG); 181 case ISD::VASTART: return LowerVASTART(Op, DAG); 182 case ISD::SMUL_LOHI: return LowerSMUL_LOHI(Op, DAG); 183 case ISD::UMUL_LOHI: return LowerUMUL_LOHI(Op, DAG); 184 // FIXME: Remove these when LegalizeDAGTypes lands. 185 case ISD::ADD: 186 case ISD::SUB: return ExpandADDSUB(Op.getNode(), DAG); 187 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 188 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG); 189 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG); 190 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 191 default: 192 llvm_unreachable("unimplemented operand"); 193 } 194 } 195 196 /// ReplaceNodeResults - Replace the results of node with an illegal result 197 /// type with new values built out of custom code. 198 void XCoreTargetLowering::ReplaceNodeResults(SDNode *N, 199 SmallVectorImpl<SDValue>&Results, 200 SelectionDAG &DAG) const { 201 switch (N->getOpcode()) { 202 default: 203 llvm_unreachable("Don't know how to custom expand this!"); 204 case ISD::ADD: 205 case ISD::SUB: 206 Results.push_back(ExpandADDSUB(N, DAG)); 207 return; 208 } 209 } 210 211 //===----------------------------------------------------------------------===// 212 // Misc Lower Operation implementation 213 //===----------------------------------------------------------------------===// 214 215 SDValue XCoreTargetLowering:: 216 LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const 217 { 218 SDLoc dl(Op); 219 SDValue Cond = DAG.getNode(ISD::SETCC, dl, MVT::i32, Op.getOperand(2), 220 Op.getOperand(3), Op.getOperand(4)); 221 return DAG.getNode(ISD::SELECT, dl, MVT::i32, Cond, Op.getOperand(0), 222 Op.getOperand(1)); 223 } 224 225 SDValue XCoreTargetLowering:: 226 getGlobalAddressWrapper(SDValue GA, const GlobalValue *GV, 227 SelectionDAG &DAG) const 228 { 229 // FIXME there is no actual debug info here 230 SDLoc dl(GA); 231 const GlobalValue *UnderlyingGV = GV; 232 // If GV is an alias then use the aliasee to determine the wrapper type 233 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 234 UnderlyingGV = GA->resolveAliasedGlobal(); 235 if (const GlobalVariable *GVar = dyn_cast<GlobalVariable>(UnderlyingGV)) { 236 if (GVar->isConstant()) 237 return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, GA); 238 return DAG.getNode(XCoreISD::DPRelativeWrapper, dl, MVT::i32, GA); 239 } 240 return DAG.getNode(XCoreISD::PCRelativeWrapper, dl, MVT::i32, GA); 241 } 242 243 SDValue XCoreTargetLowering:: 244 LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const 245 { 246 SDLoc DL(Op); 247 const GlobalAddressSDNode *GN = cast<GlobalAddressSDNode>(Op); 248 const GlobalValue *GV = GN->getGlobal(); 249 int64_t Offset = GN->getOffset(); 250 // We can only fold positive offsets that are a multiple of the word size. 251 int64_t FoldedOffset = std::max(Offset & ~3, (int64_t)0); 252 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i32, FoldedOffset); 253 GA = getGlobalAddressWrapper(GA, GV, DAG); 254 // Handle the rest of the offset. 255 if (Offset != FoldedOffset) { 256 SDValue Remaining = DAG.getConstant(Offset - FoldedOffset, MVT::i32); 257 GA = DAG.getNode(ISD::ADD, DL, MVT::i32, GA, Remaining); 258 } 259 return GA; 260 } 261 262 static inline SDValue BuildGetId(SelectionDAG &DAG, SDLoc dl) { 263 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32, 264 DAG.getConstant(Intrinsic::xcore_getid, MVT::i32)); 265 } 266 267 SDValue XCoreTargetLowering:: 268 LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const 269 { 270 SDLoc DL(Op); 271 272 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 273 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy()); 274 275 return DAG.getNode(XCoreISD::PCRelativeWrapper, DL, getPointerTy(), Result); 276 } 277 278 SDValue XCoreTargetLowering:: 279 LowerConstantPool(SDValue Op, SelectionDAG &DAG) const 280 { 281 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 282 // FIXME there isn't really debug info here 283 SDLoc dl(CP); 284 EVT PtrVT = Op.getValueType(); 285 SDValue Res; 286 if (CP->isMachineConstantPoolEntry()) { 287 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT, 288 CP->getAlignment()); 289 } else { 290 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, 291 CP->getAlignment()); 292 } 293 return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, Res); 294 } 295 296 unsigned XCoreTargetLowering::getJumpTableEncoding() const { 297 return MachineJumpTableInfo::EK_Inline; 298 } 299 300 SDValue XCoreTargetLowering:: 301 LowerBR_JT(SDValue Op, SelectionDAG &DAG) const 302 { 303 SDValue Chain = Op.getOperand(0); 304 SDValue Table = Op.getOperand(1); 305 SDValue Index = Op.getOperand(2); 306 SDLoc dl(Op); 307 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table); 308 unsigned JTI = JT->getIndex(); 309 MachineFunction &MF = DAG.getMachineFunction(); 310 const MachineJumpTableInfo *MJTI = MF.getJumpTableInfo(); 311 SDValue TargetJT = DAG.getTargetJumpTable(JT->getIndex(), MVT::i32); 312 313 unsigned NumEntries = MJTI->getJumpTables()[JTI].MBBs.size(); 314 if (NumEntries <= 32) { 315 return DAG.getNode(XCoreISD::BR_JT, dl, MVT::Other, Chain, TargetJT, Index); 316 } 317 assert((NumEntries >> 31) == 0); 318 SDValue ScaledIndex = DAG.getNode(ISD::SHL, dl, MVT::i32, Index, 319 DAG.getConstant(1, MVT::i32)); 320 return DAG.getNode(XCoreISD::BR_JT32, dl, MVT::Other, Chain, TargetJT, 321 ScaledIndex); 322 } 323 324 SDValue XCoreTargetLowering:: 325 lowerLoadWordFromAlignedBasePlusOffset(SDLoc DL, SDValue Chain, SDValue Base, 326 int64_t Offset, SelectionDAG &DAG) const 327 { 328 if ((Offset & 0x3) == 0) { 329 return DAG.getLoad(getPointerTy(), DL, Chain, Base, MachinePointerInfo(), 330 false, false, false, 0); 331 } 332 // Lower to pair of consecutive word aligned loads plus some bit shifting. 333 int32_t HighOffset = RoundUpToAlignment(Offset, 4); 334 int32_t LowOffset = HighOffset - 4; 335 SDValue LowAddr, HighAddr; 336 if (GlobalAddressSDNode *GASD = 337 dyn_cast<GlobalAddressSDNode>(Base.getNode())) { 338 LowAddr = DAG.getGlobalAddress(GASD->getGlobal(), DL, Base.getValueType(), 339 LowOffset); 340 HighAddr = DAG.getGlobalAddress(GASD->getGlobal(), DL, Base.getValueType(), 341 HighOffset); 342 } else { 343 LowAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, Base, 344 DAG.getConstant(LowOffset, MVT::i32)); 345 HighAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, Base, 346 DAG.getConstant(HighOffset, MVT::i32)); 347 } 348 SDValue LowShift = DAG.getConstant((Offset - LowOffset) * 8, MVT::i32); 349 SDValue HighShift = DAG.getConstant((HighOffset - Offset) * 8, MVT::i32); 350 351 SDValue Low = DAG.getLoad(getPointerTy(), DL, Chain, 352 LowAddr, MachinePointerInfo(), 353 false, false, false, 0); 354 SDValue High = DAG.getLoad(getPointerTy(), DL, Chain, 355 HighAddr, MachinePointerInfo(), 356 false, false, false, 0); 357 SDValue LowShifted = DAG.getNode(ISD::SRL, DL, MVT::i32, Low, LowShift); 358 SDValue HighShifted = DAG.getNode(ISD::SHL, DL, MVT::i32, High, HighShift); 359 SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, LowShifted, HighShifted); 360 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Low.getValue(1), 361 High.getValue(1)); 362 SDValue Ops[] = { Result, Chain }; 363 return DAG.getMergeValues(Ops, 2, DL); 364 } 365 366 static bool isWordAligned(SDValue Value, SelectionDAG &DAG) 367 { 368 APInt KnownZero, KnownOne; 369 DAG.ComputeMaskedBits(Value, KnownZero, KnownOne); 370 return KnownZero.countTrailingOnes() >= 2; 371 } 372 373 SDValue XCoreTargetLowering:: 374 LowerLOAD(SDValue Op, SelectionDAG &DAG) const { 375 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 376 LoadSDNode *LD = cast<LoadSDNode>(Op); 377 assert(LD->getExtensionType() == ISD::NON_EXTLOAD && 378 "Unexpected extension type"); 379 assert(LD->getMemoryVT() == MVT::i32 && "Unexpected load EVT"); 380 if (allowsUnalignedMemoryAccesses(LD->getMemoryVT())) 381 return SDValue(); 382 383 unsigned ABIAlignment = getDataLayout()-> 384 getABITypeAlignment(LD->getMemoryVT().getTypeForEVT(*DAG.getContext())); 385 // Leave aligned load alone. 386 if (LD->getAlignment() >= ABIAlignment) 387 return SDValue(); 388 389 SDValue Chain = LD->getChain(); 390 SDValue BasePtr = LD->getBasePtr(); 391 SDLoc DL(Op); 392 393 if (!LD->isVolatile()) { 394 const GlobalValue *GV; 395 int64_t Offset = 0; 396 if (DAG.isBaseWithConstantOffset(BasePtr) && 397 isWordAligned(BasePtr->getOperand(0), DAG)) { 398 SDValue NewBasePtr = BasePtr->getOperand(0); 399 Offset = cast<ConstantSDNode>(BasePtr->getOperand(1))->getSExtValue(); 400 return lowerLoadWordFromAlignedBasePlusOffset(DL, Chain, NewBasePtr, 401 Offset, DAG); 402 } 403 if (TLI.isGAPlusOffset(BasePtr.getNode(), GV, Offset) && 404 MinAlign(GV->getAlignment(), 4) == 4) { 405 SDValue NewBasePtr = DAG.getGlobalAddress(GV, DL, 406 BasePtr->getValueType(0)); 407 return lowerLoadWordFromAlignedBasePlusOffset(DL, Chain, NewBasePtr, 408 Offset, DAG); 409 } 410 } 411 412 if (LD->getAlignment() == 2) { 413 SDValue Low = DAG.getExtLoad(ISD::ZEXTLOAD, DL, MVT::i32, Chain, 414 BasePtr, LD->getPointerInfo(), MVT::i16, 415 LD->isVolatile(), LD->isNonTemporal(), 2); 416 SDValue HighAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr, 417 DAG.getConstant(2, MVT::i32)); 418 SDValue High = DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i32, Chain, 419 HighAddr, 420 LD->getPointerInfo().getWithOffset(2), 421 MVT::i16, LD->isVolatile(), 422 LD->isNonTemporal(), 2); 423 SDValue HighShifted = DAG.getNode(ISD::SHL, DL, MVT::i32, High, 424 DAG.getConstant(16, MVT::i32)); 425 SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, Low, HighShifted); 426 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Low.getValue(1), 427 High.getValue(1)); 428 SDValue Ops[] = { Result, Chain }; 429 return DAG.getMergeValues(Ops, 2, DL); 430 } 431 432 // Lower to a call to __misaligned_load(BasePtr). 433 Type *IntPtrTy = getDataLayout()->getIntPtrType(*DAG.getContext()); 434 TargetLowering::ArgListTy Args; 435 TargetLowering::ArgListEntry Entry; 436 437 Entry.Ty = IntPtrTy; 438 Entry.Node = BasePtr; 439 Args.push_back(Entry); 440 441 TargetLowering::CallLoweringInfo CLI(Chain, IntPtrTy, false, false, 442 false, false, 0, CallingConv::C, /*isTailCall=*/false, 443 /*doesNotRet=*/false, /*isReturnValueUsed=*/true, 444 DAG.getExternalSymbol("__misaligned_load", getPointerTy()), 445 Args, DAG, DL); 446 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI); 447 448 SDValue Ops[] = 449 { CallResult.first, CallResult.second }; 450 451 return DAG.getMergeValues(Ops, 2, DL); 452 } 453 454 SDValue XCoreTargetLowering:: 455 LowerSTORE(SDValue Op, SelectionDAG &DAG) const 456 { 457 StoreSDNode *ST = cast<StoreSDNode>(Op); 458 assert(!ST->isTruncatingStore() && "Unexpected store type"); 459 assert(ST->getMemoryVT() == MVT::i32 && "Unexpected store EVT"); 460 if (allowsUnalignedMemoryAccesses(ST->getMemoryVT())) { 461 return SDValue(); 462 } 463 unsigned ABIAlignment = getDataLayout()-> 464 getABITypeAlignment(ST->getMemoryVT().getTypeForEVT(*DAG.getContext())); 465 // Leave aligned store alone. 466 if (ST->getAlignment() >= ABIAlignment) { 467 return SDValue(); 468 } 469 SDValue Chain = ST->getChain(); 470 SDValue BasePtr = ST->getBasePtr(); 471 SDValue Value = ST->getValue(); 472 SDLoc dl(Op); 473 474 if (ST->getAlignment() == 2) { 475 SDValue Low = Value; 476 SDValue High = DAG.getNode(ISD::SRL, dl, MVT::i32, Value, 477 DAG.getConstant(16, MVT::i32)); 478 SDValue StoreLow = DAG.getTruncStore(Chain, dl, Low, BasePtr, 479 ST->getPointerInfo(), MVT::i16, 480 ST->isVolatile(), ST->isNonTemporal(), 481 2); 482 SDValue HighAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, BasePtr, 483 DAG.getConstant(2, MVT::i32)); 484 SDValue StoreHigh = DAG.getTruncStore(Chain, dl, High, HighAddr, 485 ST->getPointerInfo().getWithOffset(2), 486 MVT::i16, ST->isVolatile(), 487 ST->isNonTemporal(), 2); 488 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, StoreLow, StoreHigh); 489 } 490 491 // Lower to a call to __misaligned_store(BasePtr, Value). 492 Type *IntPtrTy = getDataLayout()->getIntPtrType(*DAG.getContext()); 493 TargetLowering::ArgListTy Args; 494 TargetLowering::ArgListEntry Entry; 495 496 Entry.Ty = IntPtrTy; 497 Entry.Node = BasePtr; 498 Args.push_back(Entry); 499 500 Entry.Node = Value; 501 Args.push_back(Entry); 502 503 TargetLowering::CallLoweringInfo CLI(Chain, 504 Type::getVoidTy(*DAG.getContext()), false, false, 505 false, false, 0, CallingConv::C, /*isTailCall=*/false, 506 /*doesNotRet=*/false, /*isReturnValueUsed=*/true, 507 DAG.getExternalSymbol("__misaligned_store", getPointerTy()), 508 Args, DAG, dl); 509 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI); 510 511 return CallResult.second; 512 } 513 514 SDValue XCoreTargetLowering:: 515 LowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const 516 { 517 assert(Op.getValueType() == MVT::i32 && Op.getOpcode() == ISD::SMUL_LOHI && 518 "Unexpected operand to lower!"); 519 SDLoc dl(Op); 520 SDValue LHS = Op.getOperand(0); 521 SDValue RHS = Op.getOperand(1); 522 SDValue Zero = DAG.getConstant(0, MVT::i32); 523 SDValue Hi = DAG.getNode(XCoreISD::MACCS, dl, 524 DAG.getVTList(MVT::i32, MVT::i32), Zero, Zero, 525 LHS, RHS); 526 SDValue Lo(Hi.getNode(), 1); 527 SDValue Ops[] = { Lo, Hi }; 528 return DAG.getMergeValues(Ops, 2, dl); 529 } 530 531 SDValue XCoreTargetLowering:: 532 LowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const 533 { 534 assert(Op.getValueType() == MVT::i32 && Op.getOpcode() == ISD::UMUL_LOHI && 535 "Unexpected operand to lower!"); 536 SDLoc dl(Op); 537 SDValue LHS = Op.getOperand(0); 538 SDValue RHS = Op.getOperand(1); 539 SDValue Zero = DAG.getConstant(0, MVT::i32); 540 SDValue Hi = DAG.getNode(XCoreISD::LMUL, dl, 541 DAG.getVTList(MVT::i32, MVT::i32), LHS, RHS, 542 Zero, Zero); 543 SDValue Lo(Hi.getNode(), 1); 544 SDValue Ops[] = { Lo, Hi }; 545 return DAG.getMergeValues(Ops, 2, dl); 546 } 547 548 /// isADDADDMUL - Return whether Op is in a form that is equivalent to 549 /// add(add(mul(x,y),a),b). If requireIntermediatesHaveOneUse is true then 550 /// each intermediate result in the calculation must also have a single use. 551 /// If the Op is in the correct form the constituent parts are written to Mul0, 552 /// Mul1, Addend0 and Addend1. 553 static bool 554 isADDADDMUL(SDValue Op, SDValue &Mul0, SDValue &Mul1, SDValue &Addend0, 555 SDValue &Addend1, bool requireIntermediatesHaveOneUse) 556 { 557 if (Op.getOpcode() != ISD::ADD) 558 return false; 559 SDValue N0 = Op.getOperand(0); 560 SDValue N1 = Op.getOperand(1); 561 SDValue AddOp; 562 SDValue OtherOp; 563 if (N0.getOpcode() == ISD::ADD) { 564 AddOp = N0; 565 OtherOp = N1; 566 } else if (N1.getOpcode() == ISD::ADD) { 567 AddOp = N1; 568 OtherOp = N0; 569 } else { 570 return false; 571 } 572 if (requireIntermediatesHaveOneUse && !AddOp.hasOneUse()) 573 return false; 574 if (OtherOp.getOpcode() == ISD::MUL) { 575 // add(add(a,b),mul(x,y)) 576 if (requireIntermediatesHaveOneUse && !OtherOp.hasOneUse()) 577 return false; 578 Mul0 = OtherOp.getOperand(0); 579 Mul1 = OtherOp.getOperand(1); 580 Addend0 = AddOp.getOperand(0); 581 Addend1 = AddOp.getOperand(1); 582 return true; 583 } 584 if (AddOp.getOperand(0).getOpcode() == ISD::MUL) { 585 // add(add(mul(x,y),a),b) 586 if (requireIntermediatesHaveOneUse && !AddOp.getOperand(0).hasOneUse()) 587 return false; 588 Mul0 = AddOp.getOperand(0).getOperand(0); 589 Mul1 = AddOp.getOperand(0).getOperand(1); 590 Addend0 = AddOp.getOperand(1); 591 Addend1 = OtherOp; 592 return true; 593 } 594 if (AddOp.getOperand(1).getOpcode() == ISD::MUL) { 595 // add(add(a,mul(x,y)),b) 596 if (requireIntermediatesHaveOneUse && !AddOp.getOperand(1).hasOneUse()) 597 return false; 598 Mul0 = AddOp.getOperand(1).getOperand(0); 599 Mul1 = AddOp.getOperand(1).getOperand(1); 600 Addend0 = AddOp.getOperand(0); 601 Addend1 = OtherOp; 602 return true; 603 } 604 return false; 605 } 606 607 SDValue XCoreTargetLowering:: 608 TryExpandADDWithMul(SDNode *N, SelectionDAG &DAG) const 609 { 610 SDValue Mul; 611 SDValue Other; 612 if (N->getOperand(0).getOpcode() == ISD::MUL) { 613 Mul = N->getOperand(0); 614 Other = N->getOperand(1); 615 } else if (N->getOperand(1).getOpcode() == ISD::MUL) { 616 Mul = N->getOperand(1); 617 Other = N->getOperand(0); 618 } else { 619 return SDValue(); 620 } 621 SDLoc dl(N); 622 SDValue LL, RL, AddendL, AddendH; 623 LL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 624 Mul.getOperand(0), DAG.getConstant(0, MVT::i32)); 625 RL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 626 Mul.getOperand(1), DAG.getConstant(0, MVT::i32)); 627 AddendL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 628 Other, DAG.getConstant(0, MVT::i32)); 629 AddendH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 630 Other, DAG.getConstant(1, MVT::i32)); 631 APInt HighMask = APInt::getHighBitsSet(64, 32); 632 unsigned LHSSB = DAG.ComputeNumSignBits(Mul.getOperand(0)); 633 unsigned RHSSB = DAG.ComputeNumSignBits(Mul.getOperand(1)); 634 if (DAG.MaskedValueIsZero(Mul.getOperand(0), HighMask) && 635 DAG.MaskedValueIsZero(Mul.getOperand(1), HighMask)) { 636 // The inputs are both zero-extended. 637 SDValue Hi = DAG.getNode(XCoreISD::MACCU, dl, 638 DAG.getVTList(MVT::i32, MVT::i32), AddendH, 639 AddendL, LL, RL); 640 SDValue Lo(Hi.getNode(), 1); 641 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); 642 } 643 if (LHSSB > 32 && RHSSB > 32) { 644 // The inputs are both sign-extended. 645 SDValue Hi = DAG.getNode(XCoreISD::MACCS, dl, 646 DAG.getVTList(MVT::i32, MVT::i32), AddendH, 647 AddendL, LL, RL); 648 SDValue Lo(Hi.getNode(), 1); 649 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); 650 } 651 SDValue LH, RH; 652 LH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 653 Mul.getOperand(0), DAG.getConstant(1, MVT::i32)); 654 RH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 655 Mul.getOperand(1), DAG.getConstant(1, MVT::i32)); 656 SDValue Hi = DAG.getNode(XCoreISD::MACCU, dl, 657 DAG.getVTList(MVT::i32, MVT::i32), AddendH, 658 AddendL, LL, RL); 659 SDValue Lo(Hi.getNode(), 1); 660 RH = DAG.getNode(ISD::MUL, dl, MVT::i32, LL, RH); 661 LH = DAG.getNode(ISD::MUL, dl, MVT::i32, LH, RL); 662 Hi = DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, RH); 663 Hi = DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, LH); 664 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); 665 } 666 667 SDValue XCoreTargetLowering:: 668 ExpandADDSUB(SDNode *N, SelectionDAG &DAG) const 669 { 670 assert(N->getValueType(0) == MVT::i64 && 671 (N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) && 672 "Unknown operand to lower!"); 673 674 if (N->getOpcode() == ISD::ADD) { 675 SDValue Result = TryExpandADDWithMul(N, DAG); 676 if (Result.getNode() != 0) 677 return Result; 678 } 679 680 SDLoc dl(N); 681 682 // Extract components 683 SDValue LHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 684 N->getOperand(0), DAG.getConstant(0, MVT::i32)); 685 SDValue LHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 686 N->getOperand(0), DAG.getConstant(1, MVT::i32)); 687 SDValue RHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 688 N->getOperand(1), DAG.getConstant(0, MVT::i32)); 689 SDValue RHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 690 N->getOperand(1), DAG.getConstant(1, MVT::i32)); 691 692 // Expand 693 unsigned Opcode = (N->getOpcode() == ISD::ADD) ? XCoreISD::LADD : 694 XCoreISD::LSUB; 695 SDValue Zero = DAG.getConstant(0, MVT::i32); 696 SDValue Lo = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32), 697 LHSL, RHSL, Zero); 698 SDValue Carry(Lo.getNode(), 1); 699 700 SDValue Hi = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32), 701 LHSH, RHSH, Carry); 702 SDValue Ignored(Hi.getNode(), 1); 703 // Merge the pieces 704 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); 705 } 706 707 SDValue XCoreTargetLowering:: 708 LowerVAARG(SDValue Op, SelectionDAG &DAG) const 709 { 710 // Whist llvm does not support aggregate varargs we can ignore 711 // the possibility of the ValueType being an implicit byVal vararg. 712 SDNode *Node = Op.getNode(); 713 EVT VT = Node->getValueType(0); // not an aggregate 714 SDValue InChain = Node->getOperand(0); 715 SDValue VAListPtr = Node->getOperand(1); 716 EVT PtrVT = VAListPtr.getValueType(); 717 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 718 SDLoc dl(Node); 719 SDValue VAList = DAG.getLoad(PtrVT, dl, InChain, 720 VAListPtr, MachinePointerInfo(SV), 721 false, false, false, 0); 722 // Increment the pointer, VAList, to the next vararg 723 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAList, 724 DAG.getIntPtrConstant(VT.getSizeInBits() / 8)); 725 // Store the incremented VAList to the legalized pointer 726 InChain = DAG.getStore(VAList.getValue(1), dl, nextPtr, VAListPtr, 727 MachinePointerInfo(SV), false, false, 0); 728 // Load the actual argument out of the pointer VAList 729 return DAG.getLoad(VT, dl, InChain, VAList, MachinePointerInfo(), 730 false, false, false, 0); 731 } 732 733 SDValue XCoreTargetLowering:: 734 LowerVASTART(SDValue Op, SelectionDAG &DAG) const 735 { 736 SDLoc dl(Op); 737 // vastart stores the address of the VarArgsFrameIndex slot into the 738 // memory location argument 739 MachineFunction &MF = DAG.getMachineFunction(); 740 XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>(); 741 SDValue Addr = DAG.getFrameIndex(XFI->getVarArgsFrameIndex(), MVT::i32); 742 return DAG.getStore(Op.getOperand(0), dl, Addr, Op.getOperand(1), 743 MachinePointerInfo(), false, false, 0); 744 } 745 746 SDValue XCoreTargetLowering::LowerFRAMEADDR(SDValue Op, 747 SelectionDAG &DAG) const { 748 SDLoc dl(Op); 749 // Depths > 0 not supported yet! 750 if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0) 751 return SDValue(); 752 753 MachineFunction &MF = DAG.getMachineFunction(); 754 const TargetRegisterInfo *RegInfo = getTargetMachine().getRegisterInfo(); 755 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, 756 RegInfo->getFrameRegister(MF), MVT::i32); 757 } 758 759 SDValue XCoreTargetLowering:: 760 LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const { 761 return Op.getOperand(0); 762 } 763 764 SDValue XCoreTargetLowering:: 765 LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const { 766 SDValue Chain = Op.getOperand(0); 767 SDValue Trmp = Op.getOperand(1); // trampoline 768 SDValue FPtr = Op.getOperand(2); // nested function 769 SDValue Nest = Op.getOperand(3); // 'nest' parameter value 770 771 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 772 773 // .align 4 774 // LDAPF_u10 r11, nest 775 // LDW_2rus r11, r11[0] 776 // STWSP_ru6 r11, sp[0] 777 // LDAPF_u10 r11, fptr 778 // LDW_2rus r11, r11[0] 779 // BAU_1r r11 780 // nest: 781 // .word nest 782 // fptr: 783 // .word fptr 784 SDValue OutChains[5]; 785 786 SDValue Addr = Trmp; 787 788 SDLoc dl(Op); 789 OutChains[0] = DAG.getStore(Chain, dl, DAG.getConstant(0x0a3cd805, MVT::i32), 790 Addr, MachinePointerInfo(TrmpAddr), false, false, 791 0); 792 793 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 794 DAG.getConstant(4, MVT::i32)); 795 OutChains[1] = DAG.getStore(Chain, dl, DAG.getConstant(0xd80456c0, MVT::i32), 796 Addr, MachinePointerInfo(TrmpAddr, 4), false, 797 false, 0); 798 799 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 800 DAG.getConstant(8, MVT::i32)); 801 OutChains[2] = DAG.getStore(Chain, dl, DAG.getConstant(0x27fb0a3c, MVT::i32), 802 Addr, MachinePointerInfo(TrmpAddr, 8), false, 803 false, 0); 804 805 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 806 DAG.getConstant(12, MVT::i32)); 807 OutChains[3] = DAG.getStore(Chain, dl, Nest, Addr, 808 MachinePointerInfo(TrmpAddr, 12), false, false, 809 0); 810 811 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 812 DAG.getConstant(16, MVT::i32)); 813 OutChains[4] = DAG.getStore(Chain, dl, FPtr, Addr, 814 MachinePointerInfo(TrmpAddr, 16), false, false, 815 0); 816 817 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 5); 818 } 819 820 SDValue XCoreTargetLowering:: 821 LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const { 822 SDLoc DL(Op); 823 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 824 switch (IntNo) { 825 case Intrinsic::xcore_crc8: 826 EVT VT = Op.getValueType(); 827 SDValue Data = 828 DAG.getNode(XCoreISD::CRC8, DL, DAG.getVTList(VT, VT), 829 Op.getOperand(1), Op.getOperand(2) , Op.getOperand(3)); 830 SDValue Crc(Data.getNode(), 1); 831 SDValue Results[] = { Crc, Data }; 832 return DAG.getMergeValues(Results, 2, DL); 833 } 834 return SDValue(); 835 } 836 837 //===----------------------------------------------------------------------===// 838 // Calling Convention Implementation 839 //===----------------------------------------------------------------------===// 840 841 #include "XCoreGenCallingConv.inc" 842 843 //===----------------------------------------------------------------------===// 844 // Call Calling Convention Implementation 845 //===----------------------------------------------------------------------===// 846 847 /// XCore call implementation 848 SDValue 849 XCoreTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, 850 SmallVectorImpl<SDValue> &InVals) const { 851 SelectionDAG &DAG = CLI.DAG; 852 SDLoc &dl = CLI.DL; 853 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; 854 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals; 855 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; 856 SDValue Chain = CLI.Chain; 857 SDValue Callee = CLI.Callee; 858 bool &isTailCall = CLI.IsTailCall; 859 CallingConv::ID CallConv = CLI.CallConv; 860 bool isVarArg = CLI.IsVarArg; 861 862 // XCore target does not yet support tail call optimization. 863 isTailCall = false; 864 865 // For now, only CallingConv::C implemented 866 switch (CallConv) 867 { 868 default: 869 llvm_unreachable("Unsupported calling convention"); 870 case CallingConv::Fast: 871 case CallingConv::C: 872 return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall, 873 Outs, OutVals, Ins, dl, DAG, InVals); 874 } 875 } 876 877 /// LowerCCCCallTo - functions arguments are copied from virtual 878 /// regs to (physical regs)/(stack frame), CALLSEQ_START and 879 /// CALLSEQ_END are emitted. 880 /// TODO: isTailCall, sret. 881 SDValue 882 XCoreTargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee, 883 CallingConv::ID CallConv, bool isVarArg, 884 bool isTailCall, 885 const SmallVectorImpl<ISD::OutputArg> &Outs, 886 const SmallVectorImpl<SDValue> &OutVals, 887 const SmallVectorImpl<ISD::InputArg> &Ins, 888 SDLoc dl, SelectionDAG &DAG, 889 SmallVectorImpl<SDValue> &InVals) const { 890 891 // Analyze operands of the call, assigning locations to each operand. 892 SmallVector<CCValAssign, 16> ArgLocs; 893 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 894 getTargetMachine(), ArgLocs, *DAG.getContext()); 895 896 // The ABI dictates there should be one stack slot available to the callee 897 // on function entry (for saving lr). 898 CCInfo.AllocateStack(4, 4); 899 900 CCInfo.AnalyzeCallOperands(Outs, CC_XCore); 901 902 // Get a count of how many bytes are to be pushed on the stack. 903 unsigned NumBytes = CCInfo.getNextStackOffset(); 904 905 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, 906 getPointerTy(), true), dl); 907 908 SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass; 909 SmallVector<SDValue, 12> MemOpChains; 910 911 // Walk the register/memloc assignments, inserting copies/loads. 912 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 913 CCValAssign &VA = ArgLocs[i]; 914 SDValue Arg = OutVals[i]; 915 916 // Promote the value if needed. 917 switch (VA.getLocInfo()) { 918 default: llvm_unreachable("Unknown loc info!"); 919 case CCValAssign::Full: break; 920 case CCValAssign::SExt: 921 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); 922 break; 923 case CCValAssign::ZExt: 924 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); 925 break; 926 case CCValAssign::AExt: 927 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); 928 break; 929 } 930 931 // Arguments that can be passed on register must be kept at 932 // RegsToPass vector 933 if (VA.isRegLoc()) { 934 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 935 } else { 936 assert(VA.isMemLoc()); 937 938 int Offset = VA.getLocMemOffset(); 939 940 MemOpChains.push_back(DAG.getNode(XCoreISD::STWSP, dl, MVT::Other, 941 Chain, Arg, 942 DAG.getConstant(Offset/4, MVT::i32))); 943 } 944 } 945 946 // Transform all store nodes into one single node because 947 // all store nodes are independent of each other. 948 if (!MemOpChains.empty()) 949 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 950 &MemOpChains[0], MemOpChains.size()); 951 952 // Build a sequence of copy-to-reg nodes chained together with token 953 // chain and flag operands which copy the outgoing args into registers. 954 // The InFlag in necessary since all emitted instructions must be 955 // stuck together. 956 SDValue InFlag; 957 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 958 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 959 RegsToPass[i].second, InFlag); 960 InFlag = Chain.getValue(1); 961 } 962 963 // If the callee is a GlobalAddress node (quite common, every direct call is) 964 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 965 // Likewise ExternalSymbol -> TargetExternalSymbol. 966 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 967 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32); 968 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) 969 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32); 970 971 // XCoreBranchLink = #chain, #target_address, #opt_in_flags... 972 // = Chain, Callee, Reg#1, Reg#2, ... 973 // 974 // Returns a chain & a flag for retval copy to use. 975 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 976 SmallVector<SDValue, 8> Ops; 977 Ops.push_back(Chain); 978 Ops.push_back(Callee); 979 980 // Add argument registers to the end of the list so that they are 981 // known live into the call. 982 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 983 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 984 RegsToPass[i].second.getValueType())); 985 986 if (InFlag.getNode()) 987 Ops.push_back(InFlag); 988 989 Chain = DAG.getNode(XCoreISD::BL, dl, NodeTys, &Ops[0], Ops.size()); 990 InFlag = Chain.getValue(1); 991 992 // Create the CALLSEQ_END node. 993 Chain = DAG.getCALLSEQ_END(Chain, 994 DAG.getConstant(NumBytes, getPointerTy(), true), 995 DAG.getConstant(0, getPointerTy(), true), 996 InFlag, dl); 997 InFlag = Chain.getValue(1); 998 999 // Handle result values, copying them out of physregs into vregs that we 1000 // return. 1001 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 1002 Ins, dl, DAG, InVals); 1003 } 1004 1005 /// LowerCallResult - Lower the result values of a call into the 1006 /// appropriate copies out of appropriate physical registers. 1007 SDValue 1008 XCoreTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 1009 CallingConv::ID CallConv, bool isVarArg, 1010 const SmallVectorImpl<ISD::InputArg> &Ins, 1011 SDLoc dl, SelectionDAG &DAG, 1012 SmallVectorImpl<SDValue> &InVals) const { 1013 1014 // Assign locations to each value returned by this call. 1015 SmallVector<CCValAssign, 16> RVLocs; 1016 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1017 getTargetMachine(), RVLocs, *DAG.getContext()); 1018 1019 CCInfo.AnalyzeCallResult(Ins, RetCC_XCore); 1020 1021 // Copy all of the result registers out of their specified physreg. 1022 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1023 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), 1024 RVLocs[i].getValVT(), InFlag).getValue(1); 1025 InFlag = Chain.getValue(2); 1026 InVals.push_back(Chain.getValue(0)); 1027 } 1028 1029 return Chain; 1030 } 1031 1032 //===----------------------------------------------------------------------===// 1033 // Formal Arguments Calling Convention Implementation 1034 //===----------------------------------------------------------------------===// 1035 1036 namespace { 1037 struct ArgDataPair { SDValue SDV; ISD::ArgFlagsTy Flags; }; 1038 } 1039 1040 /// XCore formal arguments implementation 1041 SDValue 1042 XCoreTargetLowering::LowerFormalArguments(SDValue Chain, 1043 CallingConv::ID CallConv, 1044 bool isVarArg, 1045 const SmallVectorImpl<ISD::InputArg> &Ins, 1046 SDLoc dl, 1047 SelectionDAG &DAG, 1048 SmallVectorImpl<SDValue> &InVals) 1049 const { 1050 switch (CallConv) 1051 { 1052 default: 1053 llvm_unreachable("Unsupported calling convention"); 1054 case CallingConv::C: 1055 case CallingConv::Fast: 1056 return LowerCCCArguments(Chain, CallConv, isVarArg, 1057 Ins, dl, DAG, InVals); 1058 } 1059 } 1060 1061 /// LowerCCCArguments - transform physical registers into 1062 /// virtual registers and generate load operations for 1063 /// arguments places on the stack. 1064 /// TODO: sret 1065 SDValue 1066 XCoreTargetLowering::LowerCCCArguments(SDValue Chain, 1067 CallingConv::ID CallConv, 1068 bool isVarArg, 1069 const SmallVectorImpl<ISD::InputArg> 1070 &Ins, 1071 SDLoc dl, 1072 SelectionDAG &DAG, 1073 SmallVectorImpl<SDValue> &InVals) const { 1074 MachineFunction &MF = DAG.getMachineFunction(); 1075 MachineFrameInfo *MFI = MF.getFrameInfo(); 1076 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 1077 1078 // Assign locations to all of the incoming arguments. 1079 SmallVector<CCValAssign, 16> ArgLocs; 1080 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1081 getTargetMachine(), ArgLocs, *DAG.getContext()); 1082 1083 CCInfo.AnalyzeFormalArguments(Ins, CC_XCore); 1084 1085 unsigned StackSlotSize = XCoreFrameLowering::stackSlotSize(); 1086 1087 unsigned LRSaveSize = StackSlotSize; 1088 1089 // All getCopyFromReg ops must precede any getMemcpys to prevent the 1090 // scheduler clobbering a register before it has been copied. 1091 // The stages are: 1092 // 1. CopyFromReg (and load) arg & vararg registers. 1093 // 2. Chain CopyFromReg nodes into a TokenFactor. 1094 // 3. Memcpy 'byVal' args & push final InVals. 1095 // 4. Chain mem ops nodes into a TokenFactor. 1096 SmallVector<SDValue, 4> CFRegNode; 1097 SmallVector<ArgDataPair, 4> ArgData; 1098 SmallVector<SDValue, 4> MemOps; 1099 1100 // 1a. CopyFromReg (and load) arg registers. 1101 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1102 1103 CCValAssign &VA = ArgLocs[i]; 1104 SDValue ArgIn; 1105 1106 if (VA.isRegLoc()) { 1107 // Arguments passed in registers 1108 EVT RegVT = VA.getLocVT(); 1109 switch (RegVT.getSimpleVT().SimpleTy) { 1110 default: 1111 { 1112 #ifndef NDEBUG 1113 errs() << "LowerFormalArguments Unhandled argument type: " 1114 << RegVT.getSimpleVT().SimpleTy << "\n"; 1115 #endif 1116 llvm_unreachable(0); 1117 } 1118 case MVT::i32: 1119 unsigned VReg = RegInfo.createVirtualRegister(&XCore::GRRegsRegClass); 1120 RegInfo.addLiveIn(VA.getLocReg(), VReg); 1121 ArgIn = DAG.getCopyFromReg(Chain, dl, VReg, RegVT); 1122 CFRegNode.push_back(ArgIn.getValue(ArgIn->getNumValues() - 1)); 1123 } 1124 } else { 1125 // sanity check 1126 assert(VA.isMemLoc()); 1127 // Load the argument to a virtual register 1128 unsigned ObjSize = VA.getLocVT().getSizeInBits()/8; 1129 if (ObjSize > StackSlotSize) { 1130 errs() << "LowerFormalArguments Unhandled argument type: " 1131 << EVT(VA.getLocVT()).getEVTString() 1132 << "\n"; 1133 } 1134 // Create the frame index object for this incoming parameter... 1135 int FI = MFI->CreateFixedObject(ObjSize, 1136 LRSaveSize + VA.getLocMemOffset(), 1137 true); 1138 1139 // Create the SelectionDAG nodes corresponding to a load 1140 //from this parameter 1141 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32); 1142 ArgIn = DAG.getLoad(VA.getLocVT(), dl, Chain, FIN, 1143 MachinePointerInfo::getFixedStack(FI), 1144 false, false, false, 0); 1145 } 1146 const ArgDataPair ADP = { ArgIn, Ins[i].Flags }; 1147 ArgData.push_back(ADP); 1148 } 1149 1150 // 1b. CopyFromReg vararg registers. 1151 if (isVarArg) { 1152 // Argument registers 1153 static const uint16_t ArgRegs[] = { 1154 XCore::R0, XCore::R1, XCore::R2, XCore::R3 1155 }; 1156 XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>(); 1157 unsigned FirstVAReg = CCInfo.getFirstUnallocated(ArgRegs, 1158 array_lengthof(ArgRegs)); 1159 if (FirstVAReg < array_lengthof(ArgRegs)) { 1160 int offset = 0; 1161 // Save remaining registers, storing higher register numbers at a higher 1162 // address 1163 for (int i = array_lengthof(ArgRegs) - 1; i >= (int)FirstVAReg; --i) { 1164 // Create a stack slot 1165 int FI = MFI->CreateFixedObject(4, offset, true); 1166 if (i == (int)FirstVAReg) { 1167 XFI->setVarArgsFrameIndex(FI); 1168 } 1169 offset -= StackSlotSize; 1170 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32); 1171 // Move argument from phys reg -> virt reg 1172 unsigned VReg = RegInfo.createVirtualRegister(&XCore::GRRegsRegClass); 1173 RegInfo.addLiveIn(ArgRegs[i], VReg); 1174 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); 1175 CFRegNode.push_back(Val.getValue(Val->getNumValues() - 1)); 1176 // Move argument from virt reg -> stack 1177 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, 1178 MachinePointerInfo(), false, false, 0); 1179 MemOps.push_back(Store); 1180 } 1181 } else { 1182 // This will point to the next argument passed via stack. 1183 XFI->setVarArgsFrameIndex( 1184 MFI->CreateFixedObject(4, LRSaveSize + CCInfo.getNextStackOffset(), 1185 true)); 1186 } 1187 } 1188 1189 // 2. chain CopyFromReg nodes into a TokenFactor. 1190 if (!CFRegNode.empty()) 1191 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &CFRegNode[0], 1192 CFRegNode.size()); 1193 1194 // 3. Memcpy 'byVal' args & push final InVals. 1195 // Aggregates passed "byVal" need to be copied by the callee. 1196 // The callee will use a pointer to this copy, rather than the original 1197 // pointer. 1198 for (SmallVectorImpl<ArgDataPair>::const_iterator ArgDI = ArgData.begin(), 1199 ArgDE = ArgData.end(); 1200 ArgDI != ArgDE; ++ArgDI) { 1201 if (ArgDI->Flags.isByVal() && ArgDI->Flags.getByValSize()) { 1202 unsigned Size = ArgDI->Flags.getByValSize(); 1203 unsigned Align = ArgDI->Flags.getByValAlign(); 1204 // Create a new object on the stack and copy the pointee into it. 1205 int FI = MFI->CreateStackObject(Size, Align, false, false); 1206 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32); 1207 InVals.push_back(FIN); 1208 MemOps.push_back(DAG.getMemcpy(Chain, dl, FIN, ArgDI->SDV, 1209 DAG.getConstant(Size, MVT::i32), 1210 Align, false, false, 1211 MachinePointerInfo(), 1212 MachinePointerInfo())); 1213 } else { 1214 InVals.push_back(ArgDI->SDV); 1215 } 1216 } 1217 1218 // 4, chain mem ops nodes into a TokenFactor. 1219 if (!MemOps.empty()) { 1220 MemOps.push_back(Chain); 1221 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &MemOps[0], 1222 MemOps.size()); 1223 } 1224 1225 return Chain; 1226 } 1227 1228 //===----------------------------------------------------------------------===// 1229 // Return Value Calling Convention Implementation 1230 //===----------------------------------------------------------------------===// 1231 1232 bool XCoreTargetLowering:: 1233 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, 1234 bool isVarArg, 1235 const SmallVectorImpl<ISD::OutputArg> &Outs, 1236 LLVMContext &Context) const { 1237 SmallVector<CCValAssign, 16> RVLocs; 1238 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), RVLocs, Context); 1239 return CCInfo.CheckReturn(Outs, RetCC_XCore); 1240 } 1241 1242 SDValue 1243 XCoreTargetLowering::LowerReturn(SDValue Chain, 1244 CallingConv::ID CallConv, bool isVarArg, 1245 const SmallVectorImpl<ISD::OutputArg> &Outs, 1246 const SmallVectorImpl<SDValue> &OutVals, 1247 SDLoc dl, SelectionDAG &DAG) const { 1248 1249 // CCValAssign - represent the assignment of 1250 // the return value to a location 1251 SmallVector<CCValAssign, 16> RVLocs; 1252 1253 // CCState - Info about the registers and stack slot. 1254 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1255 getTargetMachine(), RVLocs, *DAG.getContext()); 1256 1257 // Analyze return values. 1258 CCInfo.AnalyzeReturn(Outs, RetCC_XCore); 1259 1260 SDValue Flag; 1261 SmallVector<SDValue, 4> RetOps(1, Chain); 1262 1263 // Return on XCore is always a "retsp 0" 1264 RetOps.push_back(DAG.getConstant(0, MVT::i32)); 1265 1266 // Copy the result values into the output registers. 1267 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1268 CCValAssign &VA = RVLocs[i]; 1269 assert(VA.isRegLoc() && "Can only return in registers!"); 1270 1271 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), 1272 OutVals[i], Flag); 1273 1274 // guarantee that all emitted copies are 1275 // stuck together, avoiding something bad 1276 Flag = Chain.getValue(1); 1277 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); 1278 } 1279 1280 RetOps[0] = Chain; // Update chain. 1281 1282 // Add the flag if we have it. 1283 if (Flag.getNode()) 1284 RetOps.push_back(Flag); 1285 1286 return DAG.getNode(XCoreISD::RETSP, dl, MVT::Other, 1287 &RetOps[0], RetOps.size()); 1288 } 1289 1290 //===----------------------------------------------------------------------===// 1291 // Other Lowering Code 1292 //===----------------------------------------------------------------------===// 1293 1294 MachineBasicBlock * 1295 XCoreTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 1296 MachineBasicBlock *BB) const { 1297 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo(); 1298 DebugLoc dl = MI->getDebugLoc(); 1299 assert((MI->getOpcode() == XCore::SELECT_CC) && 1300 "Unexpected instr type to insert"); 1301 1302 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond 1303 // control-flow pattern. The incoming instruction knows the destination vreg 1304 // to set, the condition code register to branch on, the true/false values to 1305 // select between, and a branch opcode to use. 1306 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1307 MachineFunction::iterator It = BB; 1308 ++It; 1309 1310 // thisMBB: 1311 // ... 1312 // TrueVal = ... 1313 // cmpTY ccX, r1, r2 1314 // bCC copy1MBB 1315 // fallthrough --> copy0MBB 1316 MachineBasicBlock *thisMBB = BB; 1317 MachineFunction *F = BB->getParent(); 1318 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 1319 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 1320 F->insert(It, copy0MBB); 1321 F->insert(It, sinkMBB); 1322 1323 // Transfer the remainder of BB and its successor edges to sinkMBB. 1324 sinkMBB->splice(sinkMBB->begin(), BB, 1325 llvm::next(MachineBasicBlock::iterator(MI)), 1326 BB->end()); 1327 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 1328 1329 // Next, add the true and fallthrough blocks as its successors. 1330 BB->addSuccessor(copy0MBB); 1331 BB->addSuccessor(sinkMBB); 1332 1333 BuildMI(BB, dl, TII.get(XCore::BRFT_lru6)) 1334 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB); 1335 1336 // copy0MBB: 1337 // %FalseValue = ... 1338 // # fallthrough to sinkMBB 1339 BB = copy0MBB; 1340 1341 // Update machine-CFG edges 1342 BB->addSuccessor(sinkMBB); 1343 1344 // sinkMBB: 1345 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 1346 // ... 1347 BB = sinkMBB; 1348 BuildMI(*BB, BB->begin(), dl, 1349 TII.get(XCore::PHI), MI->getOperand(0).getReg()) 1350 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB) 1351 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 1352 1353 MI->eraseFromParent(); // The pseudo instruction is gone now. 1354 return BB; 1355 } 1356 1357 //===----------------------------------------------------------------------===// 1358 // Target Optimization Hooks 1359 //===----------------------------------------------------------------------===// 1360 1361 SDValue XCoreTargetLowering::PerformDAGCombine(SDNode *N, 1362 DAGCombinerInfo &DCI) const { 1363 SelectionDAG &DAG = DCI.DAG; 1364 SDLoc dl(N); 1365 switch (N->getOpcode()) { 1366 default: break; 1367 case XCoreISD::LADD: { 1368 SDValue N0 = N->getOperand(0); 1369 SDValue N1 = N->getOperand(1); 1370 SDValue N2 = N->getOperand(2); 1371 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1372 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1373 EVT VT = N0.getValueType(); 1374 1375 // canonicalize constant to RHS 1376 if (N0C && !N1C) 1377 return DAG.getNode(XCoreISD::LADD, dl, DAG.getVTList(VT, VT), N1, N0, N2); 1378 1379 // fold (ladd 0, 0, x) -> 0, x & 1 1380 if (N0C && N0C->isNullValue() && N1C && N1C->isNullValue()) { 1381 SDValue Carry = DAG.getConstant(0, VT); 1382 SDValue Result = DAG.getNode(ISD::AND, dl, VT, N2, 1383 DAG.getConstant(1, VT)); 1384 SDValue Ops[] = { Result, Carry }; 1385 return DAG.getMergeValues(Ops, 2, dl); 1386 } 1387 1388 // fold (ladd x, 0, y) -> 0, add x, y iff carry is unused and y has only the 1389 // low bit set 1390 if (N1C && N1C->isNullValue() && N->hasNUsesOfValue(0, 1)) { 1391 APInt KnownZero, KnownOne; 1392 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(), 1393 VT.getSizeInBits() - 1); 1394 DAG.ComputeMaskedBits(N2, KnownZero, KnownOne); 1395 if ((KnownZero & Mask) == Mask) { 1396 SDValue Carry = DAG.getConstant(0, VT); 1397 SDValue Result = DAG.getNode(ISD::ADD, dl, VT, N0, N2); 1398 SDValue Ops[] = { Result, Carry }; 1399 return DAG.getMergeValues(Ops, 2, dl); 1400 } 1401 } 1402 } 1403 break; 1404 case XCoreISD::LSUB: { 1405 SDValue N0 = N->getOperand(0); 1406 SDValue N1 = N->getOperand(1); 1407 SDValue N2 = N->getOperand(2); 1408 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1409 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1410 EVT VT = N0.getValueType(); 1411 1412 // fold (lsub 0, 0, x) -> x, -x iff x has only the low bit set 1413 if (N0C && N0C->isNullValue() && N1C && N1C->isNullValue()) { 1414 APInt KnownZero, KnownOne; 1415 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(), 1416 VT.getSizeInBits() - 1); 1417 DAG.ComputeMaskedBits(N2, KnownZero, KnownOne); 1418 if ((KnownZero & Mask) == Mask) { 1419 SDValue Borrow = N2; 1420 SDValue Result = DAG.getNode(ISD::SUB, dl, VT, 1421 DAG.getConstant(0, VT), N2); 1422 SDValue Ops[] = { Result, Borrow }; 1423 return DAG.getMergeValues(Ops, 2, dl); 1424 } 1425 } 1426 1427 // fold (lsub x, 0, y) -> 0, sub x, y iff borrow is unused and y has only the 1428 // low bit set 1429 if (N1C && N1C->isNullValue() && N->hasNUsesOfValue(0, 1)) { 1430 APInt KnownZero, KnownOne; 1431 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(), 1432 VT.getSizeInBits() - 1); 1433 DAG.ComputeMaskedBits(N2, KnownZero, KnownOne); 1434 if ((KnownZero & Mask) == Mask) { 1435 SDValue Borrow = DAG.getConstant(0, VT); 1436 SDValue Result = DAG.getNode(ISD::SUB, dl, VT, N0, N2); 1437 SDValue Ops[] = { Result, Borrow }; 1438 return DAG.getMergeValues(Ops, 2, dl); 1439 } 1440 } 1441 } 1442 break; 1443 case XCoreISD::LMUL: { 1444 SDValue N0 = N->getOperand(0); 1445 SDValue N1 = N->getOperand(1); 1446 SDValue N2 = N->getOperand(2); 1447 SDValue N3 = N->getOperand(3); 1448 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1449 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1450 EVT VT = N0.getValueType(); 1451 // Canonicalize multiplicative constant to RHS. If both multiplicative 1452 // operands are constant canonicalize smallest to RHS. 1453 if ((N0C && !N1C) || 1454 (N0C && N1C && N0C->getZExtValue() < N1C->getZExtValue())) 1455 return DAG.getNode(XCoreISD::LMUL, dl, DAG.getVTList(VT, VT), 1456 N1, N0, N2, N3); 1457 1458 // lmul(x, 0, a, b) 1459 if (N1C && N1C->isNullValue()) { 1460 // If the high result is unused fold to add(a, b) 1461 if (N->hasNUsesOfValue(0, 0)) { 1462 SDValue Lo = DAG.getNode(ISD::ADD, dl, VT, N2, N3); 1463 SDValue Ops[] = { Lo, Lo }; 1464 return DAG.getMergeValues(Ops, 2, dl); 1465 } 1466 // Otherwise fold to ladd(a, b, 0) 1467 SDValue Result = 1468 DAG.getNode(XCoreISD::LADD, dl, DAG.getVTList(VT, VT), N2, N3, N1); 1469 SDValue Carry(Result.getNode(), 1); 1470 SDValue Ops[] = { Carry, Result }; 1471 return DAG.getMergeValues(Ops, 2, dl); 1472 } 1473 } 1474 break; 1475 case ISD::ADD: { 1476 // Fold 32 bit expressions such as add(add(mul(x,y),a),b) -> 1477 // lmul(x, y, a, b). The high result of lmul will be ignored. 1478 // This is only profitable if the intermediate results are unused 1479 // elsewhere. 1480 SDValue Mul0, Mul1, Addend0, Addend1; 1481 if (N->getValueType(0) == MVT::i32 && 1482 isADDADDMUL(SDValue(N, 0), Mul0, Mul1, Addend0, Addend1, true)) { 1483 SDValue Ignored = DAG.getNode(XCoreISD::LMUL, dl, 1484 DAG.getVTList(MVT::i32, MVT::i32), Mul0, 1485 Mul1, Addend0, Addend1); 1486 SDValue Result(Ignored.getNode(), 1); 1487 return Result; 1488 } 1489 APInt HighMask = APInt::getHighBitsSet(64, 32); 1490 // Fold 64 bit expression such as add(add(mul(x,y),a),b) -> 1491 // lmul(x, y, a, b) if all operands are zero-extended. We do this 1492 // before type legalization as it is messy to match the operands after 1493 // that. 1494 if (N->getValueType(0) == MVT::i64 && 1495 isADDADDMUL(SDValue(N, 0), Mul0, Mul1, Addend0, Addend1, false) && 1496 DAG.MaskedValueIsZero(Mul0, HighMask) && 1497 DAG.MaskedValueIsZero(Mul1, HighMask) && 1498 DAG.MaskedValueIsZero(Addend0, HighMask) && 1499 DAG.MaskedValueIsZero(Addend1, HighMask)) { 1500 SDValue Mul0L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 1501 Mul0, DAG.getConstant(0, MVT::i32)); 1502 SDValue Mul1L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 1503 Mul1, DAG.getConstant(0, MVT::i32)); 1504 SDValue Addend0L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 1505 Addend0, DAG.getConstant(0, MVT::i32)); 1506 SDValue Addend1L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 1507 Addend1, DAG.getConstant(0, MVT::i32)); 1508 SDValue Hi = DAG.getNode(XCoreISD::LMUL, dl, 1509 DAG.getVTList(MVT::i32, MVT::i32), Mul0L, Mul1L, 1510 Addend0L, Addend1L); 1511 SDValue Lo(Hi.getNode(), 1); 1512 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); 1513 } 1514 } 1515 break; 1516 case ISD::STORE: { 1517 // Replace unaligned store of unaligned load with memmove. 1518 StoreSDNode *ST = cast<StoreSDNode>(N); 1519 if (!DCI.isBeforeLegalize() || 1520 allowsUnalignedMemoryAccesses(ST->getMemoryVT()) || 1521 ST->isVolatile() || ST->isIndexed()) { 1522 break; 1523 } 1524 SDValue Chain = ST->getChain(); 1525 1526 unsigned StoreBits = ST->getMemoryVT().getStoreSizeInBits(); 1527 if (StoreBits % 8) { 1528 break; 1529 } 1530 unsigned ABIAlignment = getDataLayout()->getABITypeAlignment( 1531 ST->getMemoryVT().getTypeForEVT(*DCI.DAG.getContext())); 1532 unsigned Alignment = ST->getAlignment(); 1533 if (Alignment >= ABIAlignment) { 1534 break; 1535 } 1536 1537 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(ST->getValue())) { 1538 if (LD->hasNUsesOfValue(1, 0) && ST->getMemoryVT() == LD->getMemoryVT() && 1539 LD->getAlignment() == Alignment && 1540 !LD->isVolatile() && !LD->isIndexed() && 1541 Chain.reachesChainWithoutSideEffects(SDValue(LD, 1))) { 1542 return DAG.getMemmove(Chain, dl, ST->getBasePtr(), 1543 LD->getBasePtr(), 1544 DAG.getConstant(StoreBits/8, MVT::i32), 1545 Alignment, false, ST->getPointerInfo(), 1546 LD->getPointerInfo()); 1547 } 1548 } 1549 break; 1550 } 1551 } 1552 return SDValue(); 1553 } 1554 1555 void XCoreTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 1556 APInt &KnownZero, 1557 APInt &KnownOne, 1558 const SelectionDAG &DAG, 1559 unsigned Depth) const { 1560 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0); 1561 switch (Op.getOpcode()) { 1562 default: break; 1563 case XCoreISD::LADD: 1564 case XCoreISD::LSUB: 1565 if (Op.getResNo() == 1) { 1566 // Top bits of carry / borrow are clear. 1567 KnownZero = APInt::getHighBitsSet(KnownZero.getBitWidth(), 1568 KnownZero.getBitWidth() - 1); 1569 } 1570 break; 1571 } 1572 } 1573 1574 //===----------------------------------------------------------------------===// 1575 // Addressing mode description hooks 1576 //===----------------------------------------------------------------------===// 1577 1578 static inline bool isImmUs(int64_t val) 1579 { 1580 return (val >= 0 && val <= 11); 1581 } 1582 1583 static inline bool isImmUs2(int64_t val) 1584 { 1585 return (val%2 == 0 && isImmUs(val/2)); 1586 } 1587 1588 static inline bool isImmUs4(int64_t val) 1589 { 1590 return (val%4 == 0 && isImmUs(val/4)); 1591 } 1592 1593 /// isLegalAddressingMode - Return true if the addressing mode represented 1594 /// by AM is legal for this target, for a load/store of the specified type. 1595 bool 1596 XCoreTargetLowering::isLegalAddressingMode(const AddrMode &AM, 1597 Type *Ty) const { 1598 if (Ty->getTypeID() == Type::VoidTyID) 1599 return AM.Scale == 0 && isImmUs(AM.BaseOffs) && isImmUs4(AM.BaseOffs); 1600 1601 const DataLayout *TD = TM.getDataLayout(); 1602 unsigned Size = TD->getTypeAllocSize(Ty); 1603 if (AM.BaseGV) { 1604 return Size >= 4 && !AM.HasBaseReg && AM.Scale == 0 && 1605 AM.BaseOffs%4 == 0; 1606 } 1607 1608 switch (Size) { 1609 case 1: 1610 // reg + imm 1611 if (AM.Scale == 0) { 1612 return isImmUs(AM.BaseOffs); 1613 } 1614 // reg + reg 1615 return AM.Scale == 1 && AM.BaseOffs == 0; 1616 case 2: 1617 case 3: 1618 // reg + imm 1619 if (AM.Scale == 0) { 1620 return isImmUs2(AM.BaseOffs); 1621 } 1622 // reg + reg<<1 1623 return AM.Scale == 2 && AM.BaseOffs == 0; 1624 default: 1625 // reg + imm 1626 if (AM.Scale == 0) { 1627 return isImmUs4(AM.BaseOffs); 1628 } 1629 // reg + reg<<2 1630 return AM.Scale == 4 && AM.BaseOffs == 0; 1631 } 1632 } 1633 1634 //===----------------------------------------------------------------------===// 1635 // XCore Inline Assembly Support 1636 //===----------------------------------------------------------------------===// 1637 1638 std::pair<unsigned, const TargetRegisterClass*> 1639 XCoreTargetLowering:: 1640 getRegForInlineAsmConstraint(const std::string &Constraint, 1641 MVT VT) const { 1642 if (Constraint.size() == 1) { 1643 switch (Constraint[0]) { 1644 default : break; 1645 case 'r': 1646 return std::make_pair(0U, &XCore::GRRegsRegClass); 1647 } 1648 } 1649 // Use the default implementation in TargetLowering to convert the register 1650 // constraint into a member of a register class. 1651 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 1652 } 1653
