| /external/llvm/lib/Target/AArch64/ |
| AArch64RegisterInfo.cpp | 109 unsigned FrameReg;
111 Offset = TFI->resolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj,
119 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, /*isDef=*/ false);
143 BaseReg, FrameReg, BaseReg, Offset);
144 FrameReg = BaseReg;
152 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, true);
|
| /external/llvm/lib/Target/Mips/ |
| Mips16RegisterInfo.cpp | 104 unsigned FrameReg;
107 FrameReg = Mips::SP;
111 FrameReg = Mips::S0;
115 FrameReg = MI.getOperand(OpNo+2).getReg();
117 FrameReg = Mips::SP;
138 !Mips16InstrInfo::validImmediate(MI.getOpcode(), FrameReg, Offset)) {
145 FrameReg = TII.loadImmediate(FrameReg, Offset, MBB, II, DL, NewImm);
149 MI.getOperand(OpNo).ChangeToRegister(FrameReg, false, false, IsKill);
|
| MipsSERegisterInfo.cpp | 92 unsigned FrameReg;
95 FrameReg = Subtarget.isABI_N64() ? Mips::SP_64 : Mips::SP;
97 FrameReg = getFrameRegister(MF);
125 BuildMI(MBB, II, DL, TII.get(ADDu), Reg).addReg(FrameReg)
128 FrameReg = Reg;
133 MI.getOperand(OpNo).ChangeToRegister(FrameReg, false, false, IsKill);
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonRegisterInfo.cpp | 136 unsigned FrameReg = getFrameRegister(MF);
181 dstReg).addReg(FrameReg).addReg(dstReg);
185 dstReg).addReg(FrameReg).addImm(Offset);
210 resReg).addReg(FrameReg).addReg(resReg);
214 resReg).addReg(FrameReg).addImm(Offset);
223 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false);
241 TII.get(Hexagon::ADD_rr), ResReg).addReg(FrameReg).
248 TII.get(Hexagon::ADD_ri), ResReg).addReg(FrameReg).
261 dstReg).addReg(FrameReg).addReg(dstReg);
269 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false)
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreRegisterInfo.cpp | 132 unsigned FrameReg = getFrameRegister(MF);
136 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false /*isDef*/);
173 .addReg(FrameReg)
179 .addReg(FrameReg)
184 .addReg(FrameReg)
194 .addReg(FrameReg)
200 .addReg(FrameReg)
205 .addReg(FrameReg)
|
| /external/llvm/lib/Target/ARM/ |
| ARMBaseRegisterInfo.cpp | 700 unsigned FrameReg;
702 int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj);
709 if (RS && FrameReg == ARM::SP && RS->isScavengingFrameIndex(FrameIndex)){
724 Done = rewriteARMFrameIndex(MI, FIOperandNum, FrameReg, Offset, TII);
727 Done = rewriteT2FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII);
747 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, false);
751 emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
755 emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
|
| ARMFrameLowering.cpp | 486 unsigned &FrameReg) const {
487 return ResolveFrameIndexReference(MF, FI, FrameReg, 0);
492 int FI, unsigned &FrameReg,
502 FrameReg = ARM::SP;
520 FrameReg = RegInfo->getFrameRegister(MF);
525 FrameReg = RegInfo->getBaseRegister();
535 FrameReg = RegInfo->getFrameRegister(MF);
544 FrameReg = RegInfo->getFrameRegister(MF);
557 FrameReg = RegInfo->getFrameRegister(MF);
562 FrameReg = RegInfo->getFrameRegister(MF)
[all...] |
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/CodeGen/AsmPrinter/ |
| DwarfCompileUnit.cpp | [all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | [all...] |
