| /external/llvm/lib/CodeGen/SelectionDAG/ |
| FunctionLoweringInfo.cpp | 66 SmallVector<ISD::OutputArg, 4> Outs;
67 GetReturnInfo(Fn->getReturnType(), Fn->getAttributes(), Outs, *TLI);
70 Outs, Fn->getContext());
|
| SelectionDAGBuilder.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | 303 const SmallVectorImpl<ISD::OutputArg> &Outs,
315 CCInfo.AnalyzeReturn(Outs, RetCC_Hexagon);
386 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
395 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
421 CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon_VarArg);
423 CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon);
432 Outs, OutVals, Ins, DAG);
460 ISD::ArgFlagsTy Flags = Outs[i].Flags
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 282 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
300 Outs, OutVals, Ins, dl, DAG, InVals);
410 const SmallVectorImpl<ISD::OutputArg> &Outs,
418 if (CallConv == CallingConv::MSP430_INTR && !Outs.empty())
426 CCInfo.AnalyzeReturn(Outs, RetCC_MSP430);
465 &Outs,
475 CCInfo.AnalyzeCallOperands(Outs, CC_MSP430);
524 ISD::ArgFlagsTy Flags = Outs[i].Flags;
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 74 /// same number of types as the Ins/Outs arrays in LowerFormalArguments,
346 const SmallVectorImpl<ISD::OutputArg> &Outs,
417 if (Outs[OIdx].Flags.isByVal() == false) {
429 // update the index for Outs
437 assert((getValueType(Ty) == Outs[OIdx].VT ||
438 (getValueType(Ty) == MVT::i8 && Outs[OIdx].VT == MVT::i16)) &&
458 unsigned align = Outs[OIdx].Flags.getByValAlign();
496 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
521 // Args.size() and Outs.size() need not match
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 165 const SmallVectorImpl<ISD::OutputArg> &Outs,
169 return LowerReturn_64(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
170 return LowerReturn_32(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
176 const SmallVectorImpl<ISD::OutputArg> &Outs,
189 CCInfo.AnalyzeReturn(Outs, RetCC_Sparc32);
239 const SmallVectorImpl<ISD::OutputArg> &Outs,
250 CCInfo.AnalyzeReturn(Outs, CC_Sparc64);
657 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
673 CCInfo.AnalyzeCallOperands(Outs, CC_Sparc32)
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 697 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
714 ArgCCInfo.AnalyzeCallOperands(Outs, CC_SystemZ);
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86FastISel.cpp | 755 SmallVector<ISD::OutputArg, 4> Outs;
756 GetReturnInfo(F.getReturnType(), F.getAttributes(), Outs, TLI);
762 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
795 if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt())
801 if (Outs[0].Flags.isSExt())
806 unsigned Op = Outs[0].Flags.isZExt() ? ISD::ZERO_EXTEND :
[all...] |
| X86ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMFastISel.cpp | [all...] |
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | [all...] |
