| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.h | 64 /// SHL, SRA, SRL - Non-constant shifts.
65 SHL, SRA, SRL
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.h | 101 SRL, SRA, SHL,
|
| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 306 SHL, SRA, SRL, ROTL, ROTR,
370 /// SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to
[all...] |
| /external/llvm/include/llvm/TableGen/ |
| Record.h | 930 enum BinaryOp { ADD, SHL, SRA, SRL, STRCONCAT, CONCAT, EQ };
[all...] |
| /system/core/libpixelflinger/codeflinger/ |
| MIPSAssembler.cpp | 399 case ASR: mMips->SRA(tmpReg, amode.reg, amode.value); break;
510 case ASR: mMips->SRA(Rd, amode.reg, amode.value); break;
542 case ASR: mMips->SRA(Rd, amode.reg, amode.value); break;
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| DAGCombiner.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 553 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
[all...] |
