| /external/llvm/lib/Target/ARM/ |
| ARMFrameLowering.h | 26 const ARMSubtarget &STI;
29 explicit ARMFrameLowering(const ARMSubtarget &sti)
30 : TargetFrameLowering(StackGrowsDown, sti.getStackAlignment(), 0, 4),
31 STI(sti) {
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| ARMBaseRegisterInfo.h | 77 const ARMSubtarget &STI;
88 explicit ARMBaseRegisterInfo(const ARMSubtarget &STI);
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| MLxExpansionPass.cpp | 383 const ARMSubtarget *STI = &Fn.getTarget().getSubtarget<ARMSubtarget>();
384 isLikeA9 = STI->isLikeA9() || STI->isSwift();
385 isSwift = STI->isSwift();
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| /external/llvm/lib/Target/Hexagon/ |
| HexagonFrameLowering.h | 21 const HexagonSubtarget &STI;
25 explicit HexagonFrameLowering(const HexagonSubtarget &sti)
26 : TargetFrameLowering(StackGrowsDown, 8, 0), STI(sti) {
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| /external/llvm/lib/Target/MSP430/ |
| MSP430FrameLowering.h | 26 const MSP430Subtarget &STI;
29 explicit MSP430FrameLowering(const MSP430Subtarget &sti)
30 : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 2, -2), STI(sti) {
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| /external/llvm/lib/Target/Mips/ |
| MipsFrameLowering.h | 26 const MipsSubtarget &STI;
29 explicit MipsFrameLowering(const MipsSubtarget &sti, unsigned Alignment)
30 : TargetFrameLowering(StackGrowsDown, Alignment, 0, Alignment), STI(sti) {}
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| MipsSEInstrInfo.cpp | 317 const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>();
319 unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
320 unsigned ADDiu = STI.isABI_N64() ? Mips::DADDiu : Mips::ADDiu;
337 const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>();
339 unsigned Size = STI.isABI_N64() ? 64 : 32;
340 unsigned LUi = STI.isABI_N64() ? Mips::LUi64 : Mips::LUi;
341 unsigned ZEROReg = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
342 const TargetRegisterClass *RC = STI.isABI_N64() ?
512 const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>();
513 unsigned ADDU = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64FrameLowering.h | 40 const AArch64Subtarget &STI;
43 explicit AArch64FrameLowering(const AArch64Subtarget &sti)
45 STI(sti) {
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| /external/llvm/lib/Target/SystemZ/ |
| SystemZFrameLowering.h | 26 const SystemZSubtarget &STI;
30 const SystemZSubtarget &sti);
|
| /external/llvm/lib/Target/X86/ |
| X86FrameLowering.h | 54 const X86Subtarget &STI;
56 explicit X86FrameLowering(const X86TargetMachine &tm, const X86Subtarget &sti)
58 sti.getStackAlignment(),
59 (sti.is64Bit() ? -8 : -4)),
60 TM(tm), STI(sti) {
|
| /external/llvm/include/llvm/MC/ |
| MCDisassembler.h | 59 MCDisassembler(const MCSubtargetInfo &STI) : GetOpInfo(0), SymbolLookUp(0),
61 STI(STI), Symbolizer(0),
104 const MCSubtargetInfo &STI;
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| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsMCCodeEmitter.cpp | 40 const MCSubtargetInfo &STI;
45 const MCSubtargetInfo &sti, bool IsLittle) :
46 MCII(mcii), Ctx(Ctx_), STI (sti), IsLittleEndian(IsLittle) {}
102 const MCSubtargetInfo &STI,
105 return new MipsMCCodeEmitter(MCII, Ctx, STI, false);
110 const MCSubtargetInfo &STI,
113 return new MipsMCCodeEmitter(MCII, Ctx, STI, true);
213 if (STI.getFeatureBits() & Mips::FeatureMicroMips) {
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| /external/llvm/include/llvm/CodeGen/ |
| TargetSchedule.h | 37 const TargetSubtargetInfo *STI;
44 TargetSchedModel(): STI(0), TII(0) {}
51 void init(const MCSchedModel &sm, const TargetSubtargetInfo *sti,
107 return STI->getWriteProcResBegin(SC);
110 return STI->getWriteProcResEnd(SC);
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| /external/llvm/lib/CodeGen/ |
| LLVMTargetMachine.cpp | 167 const MCSubtargetInfo &STI = getSubtarget<MCSubtargetInfo>();
174 MII, MRI, STI);
180 MCE = getTarget().createMCCodeEmitter(MII, MRI, STI, *Context);
198 MCCodeEmitter *MCE = getTarget().createMCCodeEmitter(MII, MRI, STI,
271 const MCSubtargetInfo &STI = getSubtarget<MCSubtargetInfo>();
273 STI, *Ctx);
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| /external/llvm/lib/MC/MCDisassembler/ |
| Disassembler.cpp | 64 const MCSubtargetInfo *STI = TheTarget->createMCSubtargetInfo(Triple, CPU,
66 if (!STI)
75 MCDisassembler *DisAsm = TheTarget->createMCDisassembler(*STI);
93 *MAI, *MII, *MRI, *STI);
100 STI, MII, Ctx, DisAsm, IP);
225 const MCSubtargetInfo *STI = DC->getSubtargetInfo();
229 AsmPrinterVariant, *MAI, *MII, *MRI, *STI);
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| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64AsmBackend.cpp | 29 const MCSubtargetInfo* STI;
33 STI(AArch64_MC::createAArch64MCSubtargetInfo(TT, "", ""))
38 delete STI;
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| /external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| PPCMCCodeEmitter.cpp | 35 const MCSubtargetInfo &STI;
40 PPCMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
42 : STI(sti), CTX(ctx), TT(STI.getTargetTriple()) {
104 const MCSubtargetInfo &STI,
106 return new PPCMCCodeEmitter(MCII, STI, Ctx);
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| /frameworks/compile/mclinker/lib/CodeGen/ |
| MCLDTargetMachine.cpp | 281 const MCSubtargetInfo &STI = getTM().getSubtarget<MCSubtargetInfo>();
286 Context->getRegisterInfo(), STI);
291 MCE = getTarget().get()->createMCCodeEmitter(MII, MRI, STI, *Context);
326 const MCSubtargetInfo &STI = getTM().getSubtarget<MCSubtargetInfo>();
328 getTarget().get()->createMCCodeEmitter(MII, MRI, STI, *Context);
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| /external/chromium_org/third_party/mesa/src/src/gallium/auxiliary/gallivm/ |
| lp_bld_debug.cpp | 217 const MCSubtargetInfo *STI = T->createMCSubtargetInfo(Triple, sys::getHostCPUName(), "");
218 OwningPtr<const MCDisassembler> DisAsm(T->createMCDisassembler(*STI));
251 T->createMCInstPrinter(AsmPrinterVariant, *AsmInfo, *MII, *MRI, *STI));
254 T->createMCInstPrinter(AsmPrinterVariant, *AsmInfo, *STI));
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| /external/llvm/lib/Target/R600/MCTargetDesc/ |
| R600MCCodeEmitter.cpp | 38 const MCSubtargetInfo &STI;
43 const MCSubtargetInfo &sti)
44 : MCII(mcii), MRI(mri), STI(sti) { }
86 const MCSubtargetInfo &STI) {
87 return new R600MCCodeEmitter(MCII, MRI, STI);
102 if (!(STI.getFeatureBits() & AMDGPU::FeatureCaymanISA)) {
135 if ((STI.getFeatureBits() & AMDGPU::FeatureR600ALUInst) &&
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| /external/mesa3d/src/gallium/auxiliary/gallivm/ |
| lp_bld_debug.cpp | 217 const MCSubtargetInfo *STI = T->createMCSubtargetInfo(Triple, sys::getHostCPUName(), "");
218 OwningPtr<const MCDisassembler> DisAsm(T->createMCDisassembler(*STI));
251 T->createMCInstPrinter(AsmPrinterVariant, *AsmInfo, *MII, *MRI, *STI));
254 T->createMCInstPrinter(AsmPrinterVariant, *AsmInfo, *STI));
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| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/MCTargetDesc/ |
| SIMCCodeEmitter.cpp | 63 const MCSubtargetInfo &STI;
67 SIMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
69 : MCII(mcii), STI(sti), Ctx(ctx) { }
126 const MCSubtargetInfo &STI,
128 return new SIMCCodeEmitter(MCII, STI, Ctx);
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| R600MCCodeEmitter.cpp | 43 const MCSubtargetInfo &STI;
48 R600MCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
50 : MCII(mcii), STI(sti), Ctx(ctx) { }
145 const MCSubtargetInfo &STI,
147 return new R600MCCodeEmitter(MCII, STI, Ctx);
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| /external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/ |
| SIMCCodeEmitter.cpp | 63 const MCSubtargetInfo &STI;
67 SIMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
69 : MCII(mcii), STI(sti), Ctx(ctx) { }
126 const MCSubtargetInfo &STI,
128 return new SIMCCodeEmitter(MCII, STI, Ctx);
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| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMAsmBackend.cpp | 43 const MCSubtargetInfo* STI;
47 : MCAsmBackend(), STI(ARM_MC::createARMMCSubtargetInfo(TT, "", "")),
51 delete STI;
57 return (STI->getFeatureBits() & ARM::HasV6T2Ops) != 0;
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