/external/llvm/lib/CodeGen/ |
ExpandPostRAPseudos.cpp | 87 assert(!MI->getOperand(2).getSubReg() && "SubIdx on physreg?"); 88 unsigned SubIdx = MI->getOperand(3).getImm(); 90 assert(SubIdx != 0 && "Invalid index for insert_subreg"); 91 unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx); 113 MI->RemoveOperand(3); // SubIdx
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MachineCopyPropagation.cpp | 120 unsigned SubIdx = TRI->getSubRegIndex(SrcSrc, Def); 121 if (!SubIdx) 123 return SubIdx == TRI->getSubRegIndex(SrcDef, Src);
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TargetRegisterInfo.cpp | 47 if (SubIdx) { 49 OS << ':' << TRI->getSubRegIndexName(SubIdx); 51 OS << ":sub(" << SubIdx << ')';
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PeepholeOptimizer.cpp | 150 unsigned SrcReg, DstReg, SubIdx; 151 if (!TII->isCoalescableExtInstr(*MI, SrcReg, DstReg, SubIdx)) 165 DstRC = TM->getRegisterInfo()->getSubClassWithSubReg(DstRC, SubIdx); 172 // If UseSrcSubIdx is Set, SubIdx also applies to SrcReg, and only uses of 173 // SrcReg:SubIdx should be replaced. 175 getSubClassWithSubReg(MRI->getRegClass(SrcReg), SubIdx) != 0; 205 // Only accept uses of SrcReg:SubIdx. 206 if (UseSrcSubIdx && UseMO.getSubReg() != SubIdx) 286 .addReg(DstReg, 0, SubIdx); 287 // SubIdx applies to both SrcReg and DstReg when UseSrcSubIdx is set [all...] |
MachineVerifier.cpp | 889 unsigned SubIdx = MO->getSubReg(); 892 if (SubIdx) { [all...] |
TwoAddressInstructionPass.cpp | [all...] |
RegisterCoalescer.cpp | 180 void updateRegDefsUses(unsigned SrcReg, unsigned DstReg, unsigned SubIdx); 335 "Cannot have a physical SubIdx"); [all...] |
/external/llvm/include/llvm/Target/ |
TargetRegisterInfo.h | 336 const char *getSubRegIndexName(unsigned SubIdx) const { 337 assert(SubIdx && SubIdx < getNumSubRegIndices() && 339 return SubRegIndexNames[SubIdx-1]; 343 /// register that are covered by SubIdx. 361 unsigned getSubRegIndexLaneMask(unsigned SubIdx) const { 362 // SubIdx == 0 is allowed, it has the lane mask ~0u. 363 assert(SubIdx < getNumSubRegIndices() && "This is not a subregister index"); 364 return SubRegIndexLaneMasks[SubIdx]; 456 /// Reg so its sub-register of index SubIdx is Reg [all...] |
/external/llvm/lib/Target/Mips/ |
MipsSEInstrInfo.cpp | 411 unsigned SubIdx = (IsI64 ? Mips::sub_32 : Mips::sub_fpeven); 417 TmpReg = getRegisterInfo().getSubReg(DstReg, SubIdx); 420 DstReg = getRegisterInfo().getSubReg(DstReg, SubIdx); 435 unsigned SubIdx = N ? Mips::sub_fpodd : Mips::sub_fpeven; 436 unsigned SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx);
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/external/llvm/lib/Target/PowerPC/ |
PPCInstrInfo.cpp | 88 unsigned &SubIdx) const { 95 SubIdx = PPC::sub_32; 494 unsigned SubIdx; 498 case PPC::PRED_EQ: SubIdx = PPC::sub_eq; SwapOps = false; break; 499 case PPC::PRED_NE: SubIdx = PPC::sub_eq; SwapOps = true; break; 500 case PPC::PRED_LT: SubIdx = PPC::sub_lt; SwapOps = false; break; 501 case PPC::PRED_GE: SubIdx = PPC::sub_lt; SwapOps = true; break; 502 case PPC::PRED_GT: SubIdx = PPC::sub_gt; SwapOps = false; break; 503 case PPC::PRED_LE: SubIdx = PPC::sub_gt; SwapOps = true; break; 504 case PPC::PRED_UN: SubIdx = PPC::sub_un; SwapOps = false; break [all...] |
/external/llvm/lib/Target/R600/ |
SIISelLowering.cpp | 714 int SubIdx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 717 return TRI.getSubClassWithSubReg(SuperClass, SubIdx); [all...] |
/external/llvm/lib/Target/ARM/ |
ARMISelDAGToDAG.cpp | [all...] |
/external/llvm/utils/TableGen/ |
AsmMatcherEmitter.cpp | [all...] |
CodeGenRegisters.cpp | 480 CodeGenSubRegIndex *SubIdx = getSubRegIndex(SI->second); 481 if (!SubIdx) 484 NewIdx->addComposite(SI->first, SubIdx); 506 // Topological signature computed from SubIdx, TopoId(SubReg). [all...] |