| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| R600ISelLowering.h | 32 const R600InstrInfo * TII;
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| SIISelLowering.h | 24 const SIInstrInfo * TII;
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| R600RegisterInfo.h | 28 const TargetInstrInfo &TII;
30 R600RegisterInfo(AMDGPUTargetMachine &tm, const TargetInstrInfo &tii);
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| SIRegisterInfo.h | 28 const TargetInstrInfo &TII;
30 SIRegisterInfo(AMDGPUTargetMachine &tm, const TargetInstrInfo &tii);
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| AMDGPUConvertToISA.cpp | 49 const AMDGPUInstrInfo * TII =
58 TII->convertToISA(MI, MF, MBB.findDebugLoc(I));
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| AMDGPURegisterInfo.h | 33 const TargetInstrInfo &TII;
36 AMDGPURegisterInfo(TargetMachine &tm, const TargetInstrInfo &tii);
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| SIAssignInterpRegs.cpp | 126 const TargetInstrInfo * TII = TM.getInstrInfo();
131 TII->get(TargetOpcode::COPY), virtReg)
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| R600ISelLowering.h | 32 const R600InstrInfo * TII;
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| SIISelLowering.h | 24 const SIInstrInfo * TII;
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| R600RegisterInfo.h | 28 const TargetInstrInfo &TII;
30 R600RegisterInfo(AMDGPUTargetMachine &tm, const TargetInstrInfo &tii);
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| SIRegisterInfo.h | 28 const TargetInstrInfo &TII;
30 SIRegisterInfo(AMDGPUTargetMachine &tm, const TargetInstrInfo &tii);
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| AMDGPUConvertToISA.cpp | 49 const AMDGPUInstrInfo * TII =
58 TII->convertToISA(MI, MF, MBB.findDebugLoc(I));
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| AMDGPURegisterInfo.h | 33 const TargetInstrInfo &TII;
36 AMDGPURegisterInfo(TargetMachine &tm, const TargetInstrInfo &tii);
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| SIAssignInterpRegs.cpp | 126 const TargetInstrInfo * TII = TM.getInstrInfo();
131 TII->get(TargetOpcode::COPY), virtReg)
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| /external/llvm/lib/CodeGen/ |
| ErlangGC.cpp | 56 const TargetInstrInfo* TII = MBB.getParent()->getTarget().getInstrInfo();
58 BuildMI(MBB, MI, DL, TII->get(TargetOpcode::GC_LABEL)).addSym(Label);
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| CriticalAntiDepBreaker.h | 37 const TargetInstrInfo *TII;
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| DeadMachineInstructionElim.cpp | 34 const TargetInstrInfo *TII;
62 if (!MI->isSafeToMove(TII, 0, SawStore) && !MI->isPHI())
90 TII = MF.getTarget().getInstrInfo();
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| ProcessImplicitDefs.cpp | 28 const TargetInstrInfo *TII;
92 UserMI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF));
144 TII = MF.getTarget().getInstrInfo();
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| /external/llvm/lib/Target/ARM/ |
| Thumb2RegisterInfo.cpp | 42 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
48 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2LDRpci))
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| ARMHazardRecognizer.cpp | 49 const ARMBaseInstrInfo &TII =
55 !(TII.getSubtarget().isLikeA9() &&
65 if (TII.isFpMLxInstruction(DefMI->getOpcode()) &&
66 (TII.canCauseFpMLxStall(MI->getOpcode()) ||
67 hasRAWHazard(DefMI, MI, TII.getRegisterInfo()))) {
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| /external/llvm/include/llvm/CodeGen/ |
| MachineSSAUpdater.h | 54 const TargetInstrInfo *TII;
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| /external/llvm/lib/Target/R600/ |
| AMDGPUConvertToISA.cpp | 49 const AMDGPUInstrInfo * TII =
58 TII->convertToISA(MI, MF, MBB.findDebugLoc(I));
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.h | 33 const TargetInstrInfo *TII;
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| /external/llvm/lib/Target/MSP430/ |
| MSP430BranchSelector.cpp | 55 const MSP430InstrInfo *TII =
70 BlockSize += TII->GetInstSizeInBytes(MBBI);
107 MBBStartOffset += TII->GetInstSizeInBytes(I);
154 TII->ReverseBranchCondition(Cond);
155 BuildMI(MBB, I, dl, TII->get(MSP430::JCC))
161 I = BuildMI(MBB, I, dl, TII->get(MSP430::Bi)).addMBB(Dest);
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| /external/llvm/lib/Target/Sparc/ |
| SparcRegisterInfo.cpp | 110 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
112 BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
114 BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
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