Home | History | Annotate | Download | only in target-mips 
      1 #if !defined(__QEMU_MIPS_EXEC_H__)
      2 #define __QEMU_MIPS_EXEC_H__
      3 
      4 //#define DEBUG_OP
      5 
      6 #include "config.h"
      7 #include "mips-defs.h"
      8 #include "dyngen-exec.h"
      9 #include "cpu-defs.h"
     10 
     11 GLOBAL_REGISTER_VARIABLE_DECL struct CPUMIPSState *env asm(AREG0);
     12 
     13 #include "cpu.h"
     14 #include "exec-all.h"
     15 
     16 #if !defined(CONFIG_USER_ONLY)
     17 #include "softmmu_exec.h"
     18 #endif /* !defined(CONFIG_USER_ONLY) */
     19 
     20 void dump_fpu(CPUState *env);
     21 void fpu_dump_state(CPUState *env, FILE *f,
     22                     int (*fpu_fprintf)(FILE *f, const char *fmt, ...),
     23                     int flags);
     24 
     25 void cpu_mips_clock_init (CPUState *env);
     26 void cpu_mips_tlb_flush (CPUState *env, int flush_global);
     27 
     28 static inline void env_to_regs(void)
     29 {
     30 }
     31 
     32 static inline void regs_to_env(void)
     33 {
     34 }
     35 
     36 static inline int cpu_has_work(CPUState *env)
     37 {
     38     int has_work = 0;
     39 
     40     /* It is implementation dependent if non-enabled interrupts
     41        wake-up the CPU, however most of the implementations only
     42        check for interrupts that can be taken. */
     43     if ((env->interrupt_request & CPU_INTERRUPT_HARD) &&
     44         cpu_mips_hw_interrupts_pending(env)) {
     45         has_work = 1;
     46     }
     47 
     48     if (env->interrupt_request & CPU_INTERRUPT_TIMER) {
     49         has_work = 1;
     50     }
     51 
     52     return has_work;
     53 }
     54 
     55 static inline int cpu_halted(CPUState *env)
     56 {
     57     if (!env->halted)
     58         return 0;
     59     if (cpu_has_work(env)) {
     60         env->halted = 0;
     61         return 0;
     62     }
     63     return EXCP_HALTED;
     64 }
     65 
     66 static inline void compute_hflags(CPUState *env)
     67 {
     68     env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 |
     69                      MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU |
     70                      MIPS_HFLAG_UX);
     71     if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
     72         !(env->CP0_Status & (1 << CP0St_ERL)) &&
     73         !(env->hflags & MIPS_HFLAG_DM)) {
     74         env->hflags |= (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU;
     75     }
     76 #if defined(TARGET_MIPS64)
     77     if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) ||
     78         (env->CP0_Status & (1 << CP0St_PX)) ||
     79         (env->CP0_Status & (1 << CP0St_UX)))
     80         env->hflags |= MIPS_HFLAG_64;
     81     if (env->CP0_Status & (1 << CP0St_UX))
     82         env->hflags |= MIPS_HFLAG_UX;
     83 #endif
     84     if ((env->CP0_Status & (1 << CP0St_CU0)) ||
     85         !(env->hflags & MIPS_HFLAG_KSU))
     86         env->hflags |= MIPS_HFLAG_CP0;
     87     if (env->CP0_Status & (1 << CP0St_CU1))
     88         env->hflags |= MIPS_HFLAG_FPU;
     89     if (env->CP0_Status & (1 << CP0St_FR))
     90         env->hflags |= MIPS_HFLAG_F64;
     91     if (env->insn_flags & ISA_MIPS32R2) {
     92         if (env->active_fpu.fcr0 & (1 << FCR0_F64))
     93             env->hflags |= MIPS_HFLAG_COP1X;
     94     } else if (env->insn_flags & ISA_MIPS32) {
     95         if (env->hflags & MIPS_HFLAG_64)
     96             env->hflags |= MIPS_HFLAG_COP1X;
     97     } else if (env->insn_flags & ISA_MIPS4) {
     98         /* All supported MIPS IV CPUs use the XX (CU3) to enable
     99            and disable the MIPS IV extensions to the MIPS III ISA.
    100            Some other MIPS IV CPUs ignore the bit, so the check here
    101            would be too restrictive for them.  */
    102         if (env->CP0_Status & (1 << CP0St_CU3))
    103             env->hflags |= MIPS_HFLAG_COP1X;
    104     }
    105 }
    106 
    107 #endif /* !defined(__QEMU_MIPS_EXEC_H__) */
    108