| /art/compiler/jni/quick/ |
| jni_compiler.cc | 190 ManagedRegister out_reg = main_jni_conv->CurrentParamRegister(); local
191 __ CreateSirtEntry(out_reg, locked_object_sirt_offset,
253 ManagedRegister out_reg = main_jni_conv->CurrentParamRegister(); local
254 __ CreateSirtEntry(out_reg, sirt_offset,
320 ManagedRegister out_reg = end_jni_conv->CurrentParamRegister(); local
321 __ Load(out_reg, saved_cookie_offset, 4);
332 ManagedRegister out_reg = end_jni_conv->CurrentParamRegister(); local
333 __ CreateSirtEntry(out_reg, locked_object_sirt_offset,
411 ManagedRegister out_reg = jni_conv->CurrentParamRegister(); local
413 __ CreateSirtEntry(out_reg, sirt_offset, in_reg, null_allowed)
435 ManagedRegister out_reg = jni_conv->CurrentParamRegister(); local
[all...] |
| /art/compiler/utils/mips/ |
| assembler_mips.cc | 840 MipsManagedRegister out_reg = mout_reg.AsMips(); local
843 CHECK(out_reg.IsCoreRegister()) << out_reg;
848 // e.g. out_reg = (handle == 0) ? 0 : (SP+handle_offset)
850 LoadFromOffset(kLoadWord, out_reg.AsCoreRegister(),
852 in_reg = out_reg;
854 if (!out_reg.Equals(in_reg)) {
855 LoadImmediate(out_reg.AsCoreRegister(), 0);
858 AddConstant(out_reg.AsCoreRegister(), SP, sirt_offset.Int32Value());
861 AddConstant(out_reg.AsCoreRegister(), SP, sirt_offset.Int32Value())
890 MipsManagedRegister out_reg = mout_reg.AsMips(); local
[all...] |
| /art/compiler/utils/arm/ |
| assembler_arm.cc | 1762 ArmManagedRegister out_reg = mout_reg.AsArm(); local
1807 ArmManagedRegister out_reg = mout_reg.AsArm(); local
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| /art/compiler/utils/x86/ |
| assembler_x86.cc | 1731 X86ManagedRegister out_reg = mout_reg.AsX86(); local
1772 X86ManagedRegister out_reg = mout_reg.AsX86(); local
[all...] |
| /external/valgrind/main/perf/ |
| tinycc.c | 17979 int nb_outputs, nb_operands, i, must_subst, out_reg; local
[all...] |
