1 /* Generated by gen_x86_insn.py rHEAD, do not edit */ 2 static const x86_info_operand insn_operands[] = { 3 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 4 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None}, 5 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 6 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 7 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 8 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None}, 9 {OPT_Mem, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 10 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 11 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 12 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_VEX, OPAP_None}, 13 {OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 14 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 15 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 16 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None}, 17 {OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 18 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEXImmSrc, OPAP_None}, 19 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 20 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_VEX, OPAP_None}, 21 {OPT_SIMDRM, OPS_256, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 22 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_VEXImmSrc, OPAP_None}, 23 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 24 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_VEX, OPAP_None}, 25 {OPT_SIMDRM, OPS_256, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 26 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 27 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 28 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None}, 29 {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 30 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 31 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 32 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None}, 33 {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 34 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 35 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 36 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None}, 37 {OPT_Mem, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 38 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 39 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 40 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None}, 41 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 42 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEXImmSrc, OPAP_None}, 43 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 44 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None}, 45 {OPT_Mem, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 46 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEXImmSrc, OPAP_None}, 47 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 48 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None}, 49 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEXImmSrc, OPAP_None}, 50 {OPT_Mem, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 51 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 52 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None}, 53 {OPT_Mem, OPS_8, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 54 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 55 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_SpareVEX, OPAP_None}, 56 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None}, 57 {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 58 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 59 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 60 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None}, 61 {OPT_Mem, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 62 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 63 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 64 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None}, 65 {OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 66 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 67 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 68 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 69 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 70 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 71 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 72 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None}, 73 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEXImmSrc, OPAP_None}, 74 {OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 75 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 76 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_VEX, OPAP_None}, 77 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_VEXImmSrc, OPAP_None}, 78 {OPT_SIMDRM, OPS_256, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 79 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 80 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None}, 81 {OPT_Mem, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 82 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEXImmSrc, OPAP_None}, 83 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 84 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None}, 85 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEXImmSrc, OPAP_None}, 86 {OPT_Mem, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 87 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_SpareVEX, OPAP_None}, 88 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None}, 89 {OPT_RM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 90 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 91 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 92 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None}, 93 {OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 94 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 95 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_SpareVEX, OPAP_None}, 96 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 97 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 98 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_SpareVEX, OPAP_None}, 99 {OPT_Mem, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 100 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 101 {OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 102 {OPT_RM, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 103 {OPT_Imm, OPS_8, 0, 0, OPTM_None, OPA_SImm, OPAP_None}, 104 {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 105 {OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 106 {OPT_Imm, OPS_8, 0, 0, OPTM_None, OPA_SImm, OPAP_None}, 107 {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 108 {OPT_RM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 109 {OPT_Imm, OPS_8, 0, 0, OPTM_None, OPA_SImm, OPAP_None}, 110 {OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 111 {OPT_RM, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 112 {OPT_Imm, OPS_16, 1, 0, OPTM_None, OPA_SImm, OPAP_SImm8}, 113 {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 114 {OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 115 {OPT_Imm, OPS_32, 1, 0, OPTM_None, OPA_SImm, OPAP_SImm8}, 116 {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 117 {OPT_RM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 118 {OPT_Imm, OPS_32, 1, 0, OPTM_None, OPA_SImm, OPAP_SImm8}, 119 {OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 120 {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 121 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 122 {OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 123 {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 124 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 125 {OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 126 {OPT_Mem, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 127 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 128 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_SpareVEX, OPAP_None}, 129 {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 130 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 131 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_SpareVEX, OPAP_None}, 132 {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 133 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 134 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_SpareVEX, OPAP_None}, 135 {OPT_Mem, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 136 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 137 {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 138 {OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 139 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 140 {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 141 {OPT_RM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 142 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 143 {OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 144 {OPT_SIMDRM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 145 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 146 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_SpareVEX, OPAP_None}, 147 {OPT_Mem, OPS_8, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 148 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 149 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_SpareVEX, OPAP_None}, 150 {OPT_Mem, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 151 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 152 {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 153 {OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 154 {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_VEX, OPAP_None}, 155 {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 156 {OPT_RM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 157 {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_VEX, OPAP_None}, 158 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 159 {OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 160 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None}, 161 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_SpareVEX, OPAP_None}, 162 {OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 163 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 164 {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 165 {OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 166 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 167 {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 168 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 169 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 170 {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 171 {OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 172 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 173 {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 174 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 175 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 176 {OPT_Mem, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 177 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 178 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 179 {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 180 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 181 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 182 {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 183 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 184 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 185 {OPT_RM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 186 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 187 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 188 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 189 {OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 190 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 191 {OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 192 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 193 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 194 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 195 {OPT_SIMDRM, OPS_256, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 196 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 197 {OPT_Mem, OPS_8, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 198 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 199 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 200 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_SpareVEX, OPAP_None}, 201 {OPT_SIMDRM, OPS_256, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 202 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 203 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_VEX, OPAP_None}, 204 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 205 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 206 {OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 207 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None}, 208 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 209 {OPT_SIMDRM, OPS_256, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 210 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_VEX, OPAP_None}, 211 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 212 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 213 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 214 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 215 {OPT_Mem, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 216 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 217 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 218 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 219 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 220 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 221 {OPT_Mem, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 222 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 223 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 224 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 225 {OPT_MemXMMIndex, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 226 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None}, 227 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 228 {OPT_MemXMMIndex, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 229 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_VEX, OPAP_None}, 230 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_SpareVEX, OPAP_None}, 231 {OPT_RM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 232 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 233 {OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 234 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 235 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 236 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_SpareVEX, OPAP_None}, 237 {OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 238 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 239 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 240 {OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 241 {OPT_XMM0, OPS_128, 0, 0, OPTM_None, OPA_None, OPAP_None}, 242 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 243 {OPT_MemXMMIndex, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 244 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None}, 245 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 246 {OPT_MemYMMIndex, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 247 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None}, 248 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 249 {OPT_MemYMMIndex, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 250 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_VEX, OPAP_None}, 251 {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 252 {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_VEX, OPAP_None}, 253 {OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 254 {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 255 {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_VEX, OPAP_None}, 256 {OPT_RM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 257 {OPT_RM, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 258 {OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 259 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 260 {OPT_RM, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 261 {OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 262 {OPT_Creg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None}, 263 {OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 264 {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 265 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 266 {OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 267 {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 268 {OPT_Creg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None}, 269 {OPT_RM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 270 {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 271 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 272 {OPT_RM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 273 {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 274 {OPT_Creg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None}, 275 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 276 {OPT_MemYMMIndex, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 277 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_VEX, OPAP_None}, 278 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 279 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None}, 280 {OPT_RM, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 281 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 282 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None}, 283 {OPT_RM, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 284 {OPT_RM, OPS_16, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 285 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 286 {OPT_RM, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 287 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 288 {OPT_RM, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 289 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 290 {OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 291 {OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 292 {OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 293 {OPT_RM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 294 {OPT_RM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 295 {OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 296 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 297 {OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 298 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 299 {OPT_RM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 300 {OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_SpareEA, OPAP_None}, 301 {OPT_Imm, OPS_8, 0, 0, OPTM_None, OPA_SImm, OPAP_None}, 302 {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_SpareEA, OPAP_None}, 303 {OPT_Imm, OPS_8, 0, 0, OPTM_None, OPA_SImm, OPAP_None}, 304 {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_SpareEA, OPAP_None}, 305 {OPT_Imm, OPS_8, 0, 0, OPTM_None, OPA_SImm, OPAP_None}, 306 {OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_SpareEA, OPAP_None}, 307 {OPT_Imm, OPS_16, 1, 0, OPTM_None, OPA_SImm, OPAP_SImm8}, 308 {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_SpareEA, OPAP_None}, 309 {OPT_Imm, OPS_32, 1, 0, OPTM_None, OPA_SImm, OPAP_SImm8}, 310 {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_SpareEA, OPAP_None}, 311 {OPT_Imm, OPS_32, 1, 0, OPTM_None, OPA_SImm, OPAP_SImm8}, 312 {OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 313 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 314 {OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 315 {OPT_Mem, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 316 {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 317 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 318 {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 319 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 320 {OPT_RM, OPS_8, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 321 {OPT_Reg, OPS_8, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 322 {OPT_Reg, OPS_8, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 323 {OPT_RM, OPS_8, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 324 {OPT_ST0, OPS_80, 0, 0, OPTM_None, OPA_None, OPAP_None}, 325 {OPT_Reg, OPS_80, 0, 0, OPTM_None, OPA_Op1Add, OPAP_None}, 326 {OPT_Reg, OPS_80, 0, 0, OPTM_None, OPA_Op1Add, OPAP_None}, 327 {OPT_ST0, OPS_80, 0, 0, OPTM_None, OPA_None, OPAP_None}, 328 {OPT_SIMDRM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 329 {OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 330 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 331 {OPT_SIMDRM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 332 {OPT_SIMDRM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 333 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 334 {OPT_Mem, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 335 {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 336 {OPT_Mem, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 337 {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 338 {OPT_Areg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None}, 339 {OPT_MemOffs, OPS_8, 1, 1, OPTM_None, OPA_EA, OPAP_None}, 340 {OPT_Areg, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None}, 341 {OPT_MemOffs, OPS_16, 1, 1, OPTM_None, OPA_EA, OPAP_None}, 342 {OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None}, 343 {OPT_MemOffs, OPS_32, 1, 1, OPTM_None, OPA_EA, OPAP_None}, 344 {OPT_Areg, OPS_64, 0, 0, OPTM_None, OPA_None, OPAP_None}, 345 {OPT_MemOffs, OPS_64, 1, 1, OPTM_None, OPA_EA, OPAP_None}, 346 {OPT_MemOffs, OPS_8, 1, 1, OPTM_None, OPA_EA, OPAP_None}, 347 {OPT_Areg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None}, 348 {OPT_MemOffs, OPS_16, 1, 1, OPTM_None, OPA_EA, OPAP_None}, 349 {OPT_Areg, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None}, 350 {OPT_MemOffs, OPS_32, 1, 1, OPTM_None, OPA_EA, OPAP_None}, 351 {OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None}, 352 {OPT_MemOffs, OPS_64, 1, 1, OPTM_None, OPA_EA, OPAP_None}, 353 {OPT_Areg, OPS_64, 0, 0, OPTM_None, OPA_None, OPAP_None}, 354 {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Op0Add, OPAP_None}, 355 {OPT_Imm, OPS_64, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 356 {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 357 {OPT_Mem, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 358 {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 359 {OPT_Mem, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 360 {OPT_Mem, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 361 {OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 362 {OPT_Areg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None}, 363 {OPT_MemOffs, OPS_8, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 364 {OPT_Areg, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None}, 365 {OPT_MemOffs, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 366 {OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None}, 367 {OPT_MemOffs, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 368 {OPT_MemOffs, OPS_8, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 369 {OPT_Areg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None}, 370 {OPT_MemOffs, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 371 {OPT_Areg, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None}, 372 {OPT_MemOffs, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 373 {OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None}, 374 {OPT_RM, OPS_8, 1, 0, OPTM_None, OPA_EA, OPAP_ShortMov}, 375 {OPT_Areg, OPS_8, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 376 {OPT_RM, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_ShortMov}, 377 {OPT_Areg, OPS_16, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 378 {OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_ShortMov}, 379 {OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 380 {OPT_RM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_ShortMov}, 381 {OPT_Areg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 382 {OPT_Areg, OPS_8, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 383 {OPT_RM, OPS_8, 1, 0, OPTM_None, OPA_EA, OPAP_ShortMov}, 384 {OPT_Areg, OPS_16, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 385 {OPT_RM, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_ShortMov}, 386 {OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 387 {OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_ShortMov}, 388 {OPT_Areg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 389 {OPT_RM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_ShortMov}, 390 {OPT_Mem, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 391 {OPT_SegReg, OPS_16, 1, 0, OPTM_None, OPA_Spare, OPAP_None}, 392 {OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 393 {OPT_SegReg, OPS_16, 1, 0, OPTM_None, OPA_Spare, OPAP_None}, 394 {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 395 {OPT_SegReg, OPS_16, 1, 0, OPTM_None, OPA_Spare, OPAP_None}, 396 {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 397 {OPT_SegReg, OPS_16, 1, 0, OPTM_None, OPA_Spare, OPAP_None}, 398 {OPT_SegReg, OPS_16, 1, 0, OPTM_None, OPA_Spare, OPAP_None}, 399 {OPT_RM, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 400 {OPT_Reg, OPS_8, 0, 0, OPTM_None, OPA_Op0Add, OPAP_None}, 401 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 402 {OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_Op0Add, OPAP_None}, 403 {OPT_Imm, OPS_16, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 404 {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Op0Add, OPAP_None}, 405 {OPT_Imm, OPS_32, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 406 {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Op0Add, OPAP_None}, 407 {OPT_Imm, OPS_64, 0, 0, OPTM_None, OPA_Imm, OPAP_None}, 408 {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Op0Add, OPAP_None}, 409 {OPT_Imm, OPS_64, 1, 0, OPTM_None, OPA_Imm, OPAP_SImm32Avail}, 410 {OPT_RM, OPS_8, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 411 {OPT_Imm, OPS_8, 0, 0, OPTM_None, OPA_Imm, OPAP_None}, 412 {OPT_RM, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 413 {OPT_Imm, OPS_16, 0, 0, OPTM_None, OPA_Imm, OPAP_None}, 414 {OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 415 {OPT_Imm, OPS_32, 0, 0, OPTM_None, OPA_Imm, OPAP_None}, 416 {OPT_RM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 417 {OPT_Imm, OPS_32, 0, 0, OPTM_None, OPA_Imm, OPAP_None}, 418 {OPT_RM, OPS_8, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 419 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 420 {OPT_RM, OPS_16, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 421 {OPT_Imm, OPS_16, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 422 {OPT_RM, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 423 {OPT_Imm, OPS_32, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 424 {OPT_RM, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 425 {OPT_Imm, OPS_32, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 426 {OPT_CR4, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 427 {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 428 {OPT_CRReg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 429 {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 430 {OPT_CRReg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 431 {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 432 {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 433 {OPT_CR4, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 434 {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 435 {OPT_CRReg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 436 {OPT_DRReg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 437 {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 438 {OPT_DRReg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 439 {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 440 {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 441 {OPT_DRReg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 442 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 443 {OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 444 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 445 {OPT_Mem, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 446 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 447 {OPT_Mem, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 448 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 449 {OPT_Mem, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 450 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 451 {OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 452 {OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 453 {OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 454 {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 455 {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 456 {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 457 {OPT_RM, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 458 {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 459 {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 460 {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 461 {OPT_RM, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 462 {OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 463 {OPT_Mem, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 464 {OPT_Mem, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 465 {OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 466 {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 467 {OPT_Mem, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 468 {OPT_Areg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None}, 469 {OPT_RM, OPS_8, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 470 {OPT_Areg, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None}, 471 {OPT_RM, OPS_16, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 472 {OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None}, 473 {OPT_RM, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 474 {OPT_Areg, OPS_64, 0, 0, OPTM_None, OPA_None, OPAP_None}, 475 {OPT_RM, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 476 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 477 {OPT_Mem, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 478 {OPT_Imm, OPS_Any, 0, 0, OPTM_None, OPA_JmpRel, OPAP_None}, 479 {OPT_Creg, OPS_32, 0, 0, OPTM_None, OPA_AdSizeR, OPAP_None}, 480 {OPT_Imm, OPS_Any, 0, 0, OPTM_Short, OPA_JmpRel, OPAP_None}, 481 {OPT_Creg, OPS_32, 0, 0, OPTM_None, OPA_AdSizeR, OPAP_None}, 482 {OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 483 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 484 {OPT_SIMDRM, OPS_256, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 485 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 486 {OPT_Imm, OPS_Any, 0, 0, OPTM_None, OPA_JmpRel, OPAP_None}, 487 {OPT_Creg, OPS_64, 0, 0, OPTM_None, OPA_AdSizeR, OPAP_None}, 488 {OPT_Imm, OPS_Any, 0, 0, OPTM_Short, OPA_JmpRel, OPAP_None}, 489 {OPT_Creg, OPS_64, 0, 0, OPTM_None, OPA_AdSizeR, OPAP_None}, 490 {OPT_Imm, OPS_Any, 0, 0, OPTM_None, OPA_JmpRel, OPAP_None}, 491 {OPT_Creg, OPS_16, 0, 0, OPTM_None, OPA_AdSizeR, OPAP_None}, 492 {OPT_Imm, OPS_Any, 0, 0, OPTM_Short, OPA_JmpRel, OPAP_None}, 493 {OPT_Creg, OPS_16, 0, 0, OPTM_None, OPA_AdSizeR, OPAP_None}, 494 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 495 {OPT_Areg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None}, 496 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 497 {OPT_Areg, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None}, 498 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 499 {OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None}, 500 {OPT_Dreg, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None}, 501 {OPT_Areg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None}, 502 {OPT_Dreg, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None}, 503 {OPT_Areg, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None}, 504 {OPT_Dreg, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None}, 505 {OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None}, 506 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 507 {OPT_Mem, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 508 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_EAVEX, OPAP_None}, 509 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 510 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_EAVEX, OPAP_None}, 511 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 512 {OPT_MemrAX, OPS_Any, 0, 0, OPTM_None, OPA_AdSizeEA, OPAP_None}, 513 {OPT_Creg, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None}, 514 {OPT_Areg, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None}, 515 {OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_Op0Add, OPAP_None}, 516 {OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_Op0Add, OPAP_None}, 517 {OPT_Areg, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None}, 518 {OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 519 {OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 520 {OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None}, 521 {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Op0Add, OPAP_None}, 522 {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Op0Add, OPAP_None}, 523 {OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None}, 524 {OPT_Areg, OPS_64, 0, 0, OPTM_None, OPA_None, OPAP_None}, 525 {OPT_Areg, OPS_64, 0, 0, OPTM_None, OPA_Op0Add, OPAP_None}, 526 {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Op0Add, OPAP_None}, 527 {OPT_Areg, OPS_64, 0, 0, OPTM_None, OPA_None, OPAP_None}, 528 {OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 529 {OPT_Mem, OPS_Any, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 530 {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 531 {OPT_Mem, OPS_Any, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 532 {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 533 {OPT_Mem, OPS_Any, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 534 {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 535 {OPT_RM, OPS_8, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 536 {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 537 {OPT_RM, OPS_16, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 538 {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 539 {OPT_RM, OPS_8, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 540 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 541 {OPT_SIMDReg, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 542 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 543 {OPT_SIMDReg, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 544 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 545 {OPT_RM, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 546 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 547 {OPT_RM, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 548 {OPT_RM, OPS_8, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 549 {OPT_Creg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None}, 550 {OPT_RM, OPS_8, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 551 {OPT_Imm1, OPS_8, 1, 0, OPTM_None, OPA_None, OPAP_None}, 552 {OPT_RM, OPS_16, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 553 {OPT_Creg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None}, 554 {OPT_RM, OPS_16, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 555 {OPT_Imm1, OPS_8, 1, 0, OPTM_None, OPA_None, OPAP_None}, 556 {OPT_RM, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 557 {OPT_Creg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None}, 558 {OPT_RM, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 559 {OPT_Imm1, OPS_8, 1, 0, OPTM_None, OPA_None, OPAP_None}, 560 {OPT_RM, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 561 {OPT_Creg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None}, 562 {OPT_RM, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 563 {OPT_Imm1, OPS_8, 1, 0, OPTM_None, OPA_None, OPAP_None}, 564 {OPT_SegReg, OPS_16, 1, 0, OPTM_None, OPA_Spare, OPAP_None}, 565 {OPT_Mem, OPS_80, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 566 {OPT_Imm, OPS_16, 1, 0, OPTM_None, OPA_JmpFar, OPAP_None}, 567 {OPT_Imm, OPS_16, 1, 0, OPTM_None, OPA_JmpFar, OPAP_None}, 568 {OPT_Imm, OPS_16, 1, 0, OPTM_None, OPA_JmpFar, OPAP_None}, 569 {OPT_Imm, OPS_32, 1, 0, OPTM_None, OPA_JmpFar, OPAP_None}, 570 {OPT_Imm, OPS_16, 1, 0, OPTM_None, OPA_JmpFar, OPAP_None}, 571 {OPT_Imm, OPS_BITS, 1, 0, OPTM_None, OPA_JmpFar, OPAP_None}, 572 {OPT_Areg, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None}, 573 {OPT_Imm, OPS_16, 1, 0, OPTM_None, OPA_Imm, OPAP_SImm8}, 574 {OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None}, 575 {OPT_Imm, OPS_32, 1, 0, OPTM_None, OPA_Imm, OPAP_SImm8}, 576 {OPT_Areg, OPS_64, 0, 0, OPTM_None, OPA_None, OPAP_None}, 577 {OPT_Imm, OPS_32, 1, 0, OPTM_None, OPA_Imm, OPAP_SImm8}, 578 {OPT_RM, OPS_16, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 579 {OPT_Imm, OPS_8, 0, 0, OPTM_None, OPA_SImm, OPAP_None}, 580 {OPT_RM, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 581 {OPT_Imm, OPS_16, 0, 0, OPTM_None, OPA_Imm, OPAP_SImm8}, 582 {OPT_RM, OPS_16, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 583 {OPT_Imm, OPS_16, 1, 0, OPTM_None, OPA_Imm, OPAP_SImm8}, 584 {OPT_RM, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 585 {OPT_Imm, OPS_8, 0, 0, OPTM_None, OPA_SImm, OPAP_None}, 586 {OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 587 {OPT_Imm, OPS_32, 0, 0, OPTM_None, OPA_Imm, OPAP_SImm8}, 588 {OPT_RM, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 589 {OPT_Imm, OPS_32, 1, 0, OPTM_None, OPA_Imm, OPAP_SImm8}, 590 {OPT_RM, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 591 {OPT_Imm, OPS_8, 0, 0, OPTM_None, OPA_SImm, OPAP_None}, 592 {OPT_RM, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 593 {OPT_Imm, OPS_32, 1, 0, OPTM_None, OPA_Imm, OPAP_SImm8}, 594 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 595 {OPT_Mem, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 596 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 597 {OPT_Mem, OPS_256, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 598 {OPT_Mem, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 599 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 600 {OPT_Mem, OPS_256, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 601 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 602 {OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 603 {OPT_RM, OPS_8, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 604 {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 605 {OPT_RM, OPS_16, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 606 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 607 {OPT_SIMDRM, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 608 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 609 {OPT_SIMDRM, OPS_256, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 610 {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 611 {OPT_Mem, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 612 {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 613 {OPT_Mem, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 614 {OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 615 {OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 616 {OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None}, 617 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 618 {OPT_Mem, OPS_80, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 619 {OPT_SegReg, OPS_16, 1, 0, OPTM_None, OPA_Spare, OPAP_None}, 620 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 621 {OPT_RM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 622 {OPT_Areg, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None}, 623 {OPT_Imm, OPS_16, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 624 {OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None}, 625 {OPT_Imm, OPS_32, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 626 {OPT_Areg, OPS_64, 0, 0, OPTM_None, OPA_None, OPAP_None}, 627 {OPT_Imm, OPS_32, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 628 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 629 {OPT_Mem, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 630 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 631 {OPT_Mem, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 632 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 633 {OPT_RM, OPS_8, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 634 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 635 {OPT_RM, OPS_8, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 636 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_SpareVEX, OPAP_None}, 637 {OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 638 {OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 639 {OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 640 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 641 {OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 642 {OPT_Imm, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_A16}, 643 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 644 {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 645 {OPT_RM, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 646 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_SpareVEX, OPAP_None}, 647 {OPT_RM, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 648 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_SpareVEX, OPAP_None}, 649 {OPT_RM, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 650 {OPT_Mem, OPS_16, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 651 {OPT_Mem, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 652 {OPT_MemEAX, OPS_Any, 0, 0, OPTM_None, OPA_None, OPAP_None}, 653 {OPT_Mem, OPS_80, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 654 {OPT_Reg, OPS_BITS, 0, 0, OPTM_None, OPA_Op0Add, OPAP_None}, 655 {OPT_RM, OPS_BITS, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 656 {OPT_SS, OPS_Any, 0, 0, OPTM_None, OPA_None, OPAP_None}, 657 {OPT_SS, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None}, 658 {OPT_SS, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None}, 659 {OPT_DS, OPS_Any, 0, 0, OPTM_None, OPA_None, OPAP_None}, 660 {OPT_DS, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None}, 661 {OPT_DS, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None}, 662 {OPT_ES, OPS_Any, 0, 0, OPTM_None, OPA_None, OPAP_None}, 663 {OPT_ES, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None}, 664 {OPT_ES, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None}, 665 {OPT_FS, OPS_Any, 0, 0, OPTM_None, OPA_None, OPAP_None}, 666 {OPT_FS, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None}, 667 {OPT_FS, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None}, 668 {OPT_GS, OPS_Any, 0, 0, OPTM_None, OPA_None, OPAP_None}, 669 {OPT_GS, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None}, 670 {OPT_GS, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None}, 671 {OPT_Mem, OPS_Any, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 672 {OPT_ImmNotSegOff, OPS_Any, 0, 0, OPTM_None, OPA_JmpRel, OPAP_None}, 673 {OPT_ImmNotSegOff, OPS_16, 0, 0, OPTM_None, OPA_JmpRel, OPAP_None}, 674 {OPT_ImmNotSegOff, OPS_32, 0, 0, OPTM_None, OPA_JmpRel, OPAP_None}, 675 {OPT_Imm, OPS_16, 0, 0, OPTM_Near, OPA_JmpRel, OPAP_None}, 676 {OPT_Imm, OPS_32, 0, 0, OPTM_Near, OPA_JmpRel, OPAP_None}, 677 {OPT_Imm, OPS_Any, 0, 0, OPTM_Near, OPA_JmpRel, OPAP_None}, 678 {OPT_Reg, OPS_BITS, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 679 {OPT_RM, OPS_16, 0, 0, OPTM_Near, OPA_EA, OPAP_None}, 680 {OPT_RM, OPS_32, 0, 0, OPTM_Near, OPA_EA, OPAP_None}, 681 {OPT_RM, OPS_64, 0, 0, OPTM_Near, OPA_EA, OPAP_None}, 682 {OPT_Mem, OPS_Any, 0, 0, OPTM_Near, OPA_EA, OPAP_None}, 683 {OPT_Mem, OPS_16, 0, 0, OPTM_Far, OPA_EA, OPAP_None}, 684 {OPT_Mem, OPS_32, 0, 0, OPTM_Far, OPA_EA, OPAP_None}, 685 {OPT_Mem, OPS_64, 0, 0, OPTM_Far, OPA_EA, OPAP_None}, 686 {OPT_Mem, OPS_Any, 0, 0, OPTM_Far, OPA_EA, OPAP_None}, 687 {OPT_Imm, OPS_16, 0, 0, OPTM_Far, OPA_JmpFar, OPAP_None}, 688 {OPT_Imm, OPS_32, 0, 0, OPTM_Far, OPA_JmpFar, OPAP_None}, 689 {OPT_Imm, OPS_Any, 0, 0, OPTM_Far, OPA_JmpFar, OPAP_None}, 690 {OPT_Imm, OPS_16, 0, 0, OPTM_None, OPA_JmpFar, OPAP_None}, 691 {OPT_Imm, OPS_32, 0, 0, OPTM_None, OPA_JmpFar, OPAP_None}, 692 {OPT_Imm, OPS_Any, 0, 0, OPTM_None, OPA_JmpFar, OPAP_None}, 693 {OPT_Reg, OPS_80, 0, 0, OPTM_To, OPA_Op1Add, OPAP_None}, 694 {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Op1Add, OPAP_None}, 695 {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Op1Add, OPAP_None}, 696 {OPT_Mem, OPS_BITS, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 697 {OPT_Imm, OPS_16, 0, 0, OPTM_None, OPA_JmpRel, OPAP_None}, 698 {OPT_Imm, OPS_32, 0, 0, OPTM_None, OPA_JmpRel, OPAP_None}, 699 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_SImm, OPAP_None}, 700 {OPT_Imm, OPS_BITS, 1, 0, OPTM_None, OPA_Imm, OPAP_SImm8}, 701 {OPT_Imm, OPS_32, 0, 0, OPTM_None, OPA_SImm, OPAP_None}, 702 {OPT_CS, OPS_Any, 0, 0, OPTM_None, OPA_None, OPAP_None}, 703 {OPT_CS, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None}, 704 {OPT_CS, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None} 705 }; 706 707 static const x86_insn_info empty_insn[] = { 708 { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0 } 709 }; 710 711 static const x86_insn_info not64_insn[] = { 712 { SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0 } 713 }; 714 715 static const x86_insn_info onebyte_insn[] = { 716 { SUF_Z, 0, 0, 0, 0, {MOD_Op0Add, MOD_OpSizeR, MOD_DOpS64R}, 0, 0, 0, 1, {0x00, 0, 0}, 0, 0, 0 } 717 }; 718 719 static const x86_insn_info onebyte_prefix_insn[] = { 720 { SUF_Z, 0, 0, 0, 0, {MOD_PreAdd, MOD_Op0Add, 0}, 0, 0, 0x00, 1, {0x00, 0, 0}, 0, 0, 0 } 721 }; 722 723 static const x86_insn_info twobyte_insn[] = { 724 { SUF_L|SUF_Q|SUF_Z, 0, 0, 0, 0, {MOD_Op0Add, MOD_Op1Add, 0}, 0, 0, 0, 2, {0x00, 0x00, 0}, 0, 0, 0 } 725 }; 726 727 static const x86_insn_info threebyte_insn[] = { 728 { SUF_Z, 0, 0, 0, 0, {MOD_Op0Add, MOD_Op1Add, MOD_Op2Add}, 0, 0, 0, 3, {0x00, 0x00, 0x00}, 0, 0, 0 } 729 }; 730 731 static const x86_insn_info onebytemem_insn[] = { 732 { SUF_L|SUF_Q|SUF_S|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, MOD_Op0Add, 0}, 0, 0, 0, 1, {0x00, 0, 0}, 0, 1, 668 } 733 }; 734 735 static const x86_insn_info twobytemem_insn[] = { 736 { SUF_L|SUF_Q|SUF_S|SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, MOD_Op0Add, MOD_Op1Add}, 0, 0, 0, 2, {0x00, 0x00, 0}, 0, 1, 526 } 737 }; 738 739 static const x86_insn_info mov_insn[] = { 740 { SUF_B|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xA0, 0, 0}, 0, 2, 359 }, 741 { SUF_W|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 361 }, 742 { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 363 }, 743 { SUF_B|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xA2, 0, 0}, 0, 2, 365 }, 744 { SUF_W|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 367 }, 745 { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 369 }, 746 { SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xA0, 0, 0}, 0, 2, 335 }, 747 { SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 337 }, 748 { SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 339 }, 749 { SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 341 }, 750 { SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xA2, 0, 0}, 0, 2, 343 }, 751 { SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 345 }, 752 { SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 347 }, 753 { SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 349 }, 754 { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x88, 0xA2, 0}, 0, 2, 371 }, 755 { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x89, 0xA3, 0}, 0, 2, 373 }, 756 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x89, 0xA3, 0}, 0, 2, 375 }, 757 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x89, 0xA3, 0}, 0, 2, 377 }, 758 { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x88, 0, 0}, 0, 2, 317 }, 759 { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x89, 0, 0}, 0, 2, 254 }, 760 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x89, 0, 0}, 0, 2, 260 }, 761 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x89, 0, 0}, 0, 2, 266 }, 762 { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x8A, 0xA0, 0}, 0, 2, 379 }, 763 { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x8B, 0xA1, 0}, 0, 2, 381 }, 764 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x8B, 0xA1, 0}, 0, 2, 383 }, 765 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x8B, 0xA1, 0}, 0, 2, 385 }, 766 { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x8A, 0, 0}, 0, 2, 319 }, 767 { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x8B, 0, 0}, 0, 2, 98 }, 768 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x8B, 0, 0}, 0, 2, 101 }, 769 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x8B, 0, 0}, 0, 2, 104 }, 770 { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x8C, 0, 0}, 0, 2, 387 }, 771 { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x8C, 0, 0}, 0, 2, 389 }, 772 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x8C, 0, 0}, 0, 2, 391 }, 773 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x8C, 0, 0}, 0, 2, 393 }, 774 { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x8E, 0, 0}, 0, 2, 395 }, 775 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x8E, 0, 0}, 0, 2, 390 }, 776 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x8E, 0, 0}, 0, 2, 392 }, 777 { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xB0, 0, 0}, 0, 2, 397 }, 778 { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xB8, 0, 0}, 0, 2, 399 }, 779 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xB8, 0, 0}, 0, 2, 401 }, 780 { GAS_ILLEGAL|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xB8, 0, 0}, 0, 2, 403 }, 781 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xB8, 0xC7, 0}, 0, 2, 405 }, 782 { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xC6, 0, 0}, 0, 2, 407 }, 783 { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xC7, 0, 0}, 0, 2, 409 }, 784 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xC7, 0, 0}, 0, 2, 411 }, 785 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xC7, 0, 0}, 0, 2, 413 }, 786 { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xC6, 0, 0}, 0, 2, 415 }, 787 { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xC7, 0, 0}, 0, 2, 417 }, 788 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xC7, 0, 0}, 0, 2, 419 }, 789 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xC7, 0, 0}, 0, 2, 421 }, 790 { SUF_L|SUF_Z, NOT_64, CPU_586, CPU_Priv, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x22, 0}, 0, 2, 423 }, 791 { SUF_L|SUF_Z, NOT_64, CPU_386, CPU_Priv, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x22, 0}, 0, 2, 425 }, 792 { SUF_Q|SUF_Z, ONLY_64, CPU_Priv, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x22, 0}, 0, 2, 427 }, 793 { SUF_L|SUF_Z, NOT_64, CPU_586, CPU_Priv, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x20, 0}, 0, 2, 429 }, 794 { SUF_L|SUF_Z, NOT_64, CPU_386, CPU_Priv, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x20, 0}, 0, 2, 424 }, 795 { SUF_Q|SUF_Z, ONLY_64, CPU_Priv, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x20, 0}, 0, 2, 431 }, 796 { SUF_L|SUF_Z, NOT_64, CPU_386, CPU_Priv, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x23, 0}, 0, 2, 433 }, 797 { SUF_Q|SUF_Z, ONLY_64, CPU_Priv, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x23, 0}, 0, 2, 435 }, 798 { SUF_L|SUF_Z, NOT_64, CPU_386, CPU_Priv, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x21, 0}, 0, 2, 434 }, 799 { SUF_Q|SUF_Z, ONLY_64, CPU_Priv, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x21, 0}, 0, 2, 437 }, 800 { GAS_ONLY|SUF_Q|SUF_Z, 0, CPU_MMX, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x6F, 0}, 0, 2, 140 }, 801 { GAS_ONLY|SUF_Q|SUF_Z, ONLY_64, CPU_MMX, 0, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0x6E, 0}, 0, 2, 289 }, 802 { GAS_ONLY|SUF_Q|SUF_Z, 0, CPU_MMX, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x7F, 0}, 0, 2, 325 }, 803 { GAS_ONLY|SUF_Q|SUF_Z, ONLY_64, CPU_MMX, 0, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0x7E, 0}, 0, 2, 291 }, 804 { GAS_ONLY|SUF_Q|SUF_Z, 0, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0xF3, 2, {0x0F, 0x7E, 0}, 0, 2, 64 }, 805 { GAS_ONLY|SUF_Q|SUF_Z, 0, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0xF3, 2, {0x0F, 0x7E, 0}, 0, 2, 327 }, 806 { GAS_ONLY|SUF_Q|SUF_Z, ONLY_64, CPU_SSE2, 0, 0, {0, 0, 0}, 64, 0, 0x66, 2, {0x0F, 0x6E, 0}, 0, 2, 295 }, 807 { GAS_ONLY|SUF_Q|SUF_Z, 0, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0x66, 2, {0x0F, 0xD6, 0}, 0, 2, 329 }, 808 { GAS_ONLY|SUF_Q|SUF_Z, ONLY_64, CPU_SSE2, 0, 0, {0, 0, 0}, 64, 0, 0x66, 2, {0x0F, 0x7E, 0}, 0, 2, 182 } 809 }; 810 811 static const x86_insn_info movabs_insn[] = { 812 { SUF_B|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xA0, 0, 0}, 0, 2, 335 }, 813 { SUF_W|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 337 }, 814 { SUF_L|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 339 }, 815 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 341 }, 816 { SUF_B|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xA2, 0, 0}, 0, 2, 343 }, 817 { SUF_W|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 345 }, 818 { SUF_L|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 347 }, 819 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 349 }, 820 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xB8, 0, 0}, 0, 2, 351 } 821 }; 822 823 static const x86_insn_info movszx_insn[] = { 824 { SUF_B|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 599 }, 825 { SUF_B|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 531 }, 826 { SUF_B|SUF_Z, ONLY_64, 0, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 535 }, 827 { SUF_W|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 2, {0x0F, 0x01, 0}, 0, 2, 533 }, 828 { SUF_W|SUF_Z, ONLY_64, 0, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 2, {0x0F, 0x01, 0}, 0, 2, 601 } 829 }; 830 831 static const x86_insn_info movsxd_insn[] = { 832 { SUF_L|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x63, 0, 0}, 0, 2, 641 } 833 }; 834 835 static const x86_insn_info push_insn[] = { 836 { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0x50, 0, 0}, 0, 1, 651 }, 837 { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 1, {0x50, 0, 0}, 0, 1, 399 }, 838 { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x50, 0, 0}, 0, 1, 401 }, 839 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0x50, 0, 0}, 0, 1, 351 }, 840 { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0xFF, 0, 0}, 6, 1, 652 }, 841 { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 1, {0xFF, 0, 0}, 6, 1, 281 }, 842 { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xFF, 0, 0}, 6, 1, 277 }, 843 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0xFF, 0, 0}, 6, 1, 280 }, 844 { GAS_ILLEGAL|SUF_Z, 0, CPU_186, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0x6A, 0, 0}, 0, 1, 100 }, 845 { GAS_ONLY|SUF_Z, 0, CPU_186, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0x6A, 0, 0}, 0, 1, 696 }, 846 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 64, 0, 1, {0x6A, 0x68, 0}, 0, 1, 112 }, 847 { GAS_ILLEGAL|SUF_Z, NOT_64, CPU_186, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x6A, 0x68, 0}, 0, 1, 697 }, 848 { SUF_W|SUF_Z, 0, CPU_186, 0, 0, {0, 0, 0}, 16, 64, 0, 1, {0x6A, 0x68, 0}, 0, 1, 570 }, 849 { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x6A, 0x68, 0}, 0, 1, 572 }, 850 { GAS_ILLEGAL|SUF_Z, 0, CPU_186, 0, 0, {0, 0, 0}, 16, 64, 0, 1, {0x68, 0, 0}, 0, 1, 410 }, 851 { GAS_ILLEGAL|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x68, 0, 0}, 0, 1, 412 }, 852 { GAS_ILLEGAL|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 64, 0, 1, {0x68, 0, 0}, 0, 1, 698 }, 853 { SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x0E, 0, 0}, 0, 1, 699 }, 854 { SUF_W|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x0E, 0, 0}, 0, 1, 700 }, 855 { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x0E, 0, 0}, 0, 1, 701 }, 856 { SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x16, 0, 0}, 0, 1, 653 }, 857 { SUF_W|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x16, 0, 0}, 0, 1, 654 }, 858 { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x16, 0, 0}, 0, 1, 655 }, 859 { SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x1E, 0, 0}, 0, 1, 656 }, 860 { SUF_W|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x1E, 0, 0}, 0, 1, 657 }, 861 { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x1E, 0, 0}, 0, 1, 658 }, 862 { SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x06, 0, 0}, 0, 1, 659 }, 863 { SUF_W|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x06, 0, 0}, 0, 1, 660 }, 864 { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x06, 0, 0}, 0, 1, 661 }, 865 { SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0xA0, 0}, 0, 1, 662 }, 866 { SUF_W|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 16, 0, 0, 2, {0x0F, 0xA0, 0}, 0, 1, 663 }, 867 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0xA0, 0}, 0, 1, 664 }, 868 { SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0xA8, 0}, 0, 1, 665 }, 869 { SUF_W|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 16, 0, 0, 2, {0x0F, 0xA8, 0}, 0, 1, 666 }, 870 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0xA8, 0}, 0, 1, 667 } 871 }; 872 873 static const x86_insn_info pop_insn[] = { 874 { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0x58, 0, 0}, 0, 1, 651 }, 875 { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 1, {0x58, 0, 0}, 0, 1, 399 }, 876 { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x58, 0, 0}, 0, 1, 401 }, 877 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0x58, 0, 0}, 0, 1, 351 }, 878 { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0x8F, 0, 0}, 0, 1, 652 }, 879 { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 1, {0x8F, 0, 0}, 0, 1, 281 }, 880 { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x8F, 0, 0}, 0, 1, 277 }, 881 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0x8F, 0, 0}, 0, 1, 280 }, 882 { SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x17, 0, 0}, 0, 1, 653 }, 883 { SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x17, 0, 0}, 0, 1, 654 }, 884 { SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x17, 0, 0}, 0, 1, 655 }, 885 { SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x1F, 0, 0}, 0, 1, 656 }, 886 { SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x1F, 0, 0}, 0, 1, 657 }, 887 { SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x1F, 0, 0}, 0, 1, 658 }, 888 { SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x07, 0, 0}, 0, 1, 659 }, 889 { SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x07, 0, 0}, 0, 1, 660 }, 890 { SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x07, 0, 0}, 0, 1, 661 }, 891 { SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0xA1, 0}, 0, 1, 662 }, 892 { SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 16, 0, 0, 2, {0x0F, 0xA1, 0}, 0, 1, 663 }, 893 { SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0xA1, 0}, 0, 1, 664 }, 894 { SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0xA9, 0}, 0, 1, 665 }, 895 { SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 16, 0, 0, 2, {0x0F, 0xA9, 0}, 0, 1, 666 }, 896 { SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0xA9, 0}, 0, 1, 667 } 897 }; 898 899 static const x86_insn_info xchg_insn[] = { 900 { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x86, 0, 0}, 0, 2, 317 }, 901 { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x86, 0, 0}, 0, 2, 319 }, 902 { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x90, 0, 0}, 0, 2, 511 }, 903 { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x90, 0, 0}, 0, 2, 513 }, 904 { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x87, 0, 0}, 0, 2, 254 }, 905 { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x87, 0, 0}, 0, 2, 98 }, 906 { SUF_L|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x87, 0, 0}, 0, 2, 515 }, 907 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x90, 0, 0}, 0, 2, 517 }, 908 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x90, 0, 0}, 0, 2, 519 }, 909 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x87, 0, 0}, 0, 2, 260 }, 910 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x87, 0, 0}, 0, 2, 101 }, 911 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x90, 0, 0}, 0, 2, 521 }, 912 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x90, 0, 0}, 0, 2, 350 }, 913 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x90, 0, 0}, 0, 2, 523 }, 914 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x87, 0, 0}, 0, 2, 266 }, 915 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x87, 0, 0}, 0, 2, 104 } 916 }; 917 918 static const x86_insn_info in_insn[] = { 919 { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xE4, 0, 0}, 0, 2, 492 }, 920 { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xE5, 0, 0}, 0, 2, 494 }, 921 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xE5, 0, 0}, 0, 2, 613 }, 922 { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xEC, 0, 0}, 0, 2, 498 }, 923 { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xED, 0, 0}, 0, 2, 500 }, 924 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xED, 0, 0}, 0, 2, 496 }, 925 { GAS_ONLY|SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xE4, 0, 0}, 0, 1, 3 }, 926 { GAS_ONLY|SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xE5, 0, 0}, 0, 1, 3 }, 927 { GAS_ONLY|SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xE5, 0, 0}, 0, 1, 3 }, 928 { GAS_ONLY|SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xEC, 0, 0}, 0, 1, 497 }, 929 { GAS_ONLY|SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xED, 0, 0}, 0, 1, 497 }, 930 { GAS_ONLY|SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xED, 0, 0}, 0, 1, 497 } 931 }; 932 933 static const x86_insn_info out_insn[] = { 934 { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xE6, 0, 0}, 0, 2, 491 }, 935 { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xE7, 0, 0}, 0, 2, 493 }, 936 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xE7, 0, 0}, 0, 2, 495 }, 937 { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xEE, 0, 0}, 0, 2, 497 }, 938 { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xEF, 0, 0}, 0, 2, 499 }, 939 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xEF, 0, 0}, 0, 2, 501 }, 940 { GAS_ONLY|SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xE6, 0, 0}, 0, 1, 3 }, 941 { GAS_ONLY|SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xE7, 0, 0}, 0, 1, 3 }, 942 { GAS_ONLY|SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xE7, 0, 0}, 0, 1, 3 }, 943 { GAS_ONLY|SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xEE, 0, 0}, 0, 1, 497 }, 944 { GAS_ONLY|SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xEF, 0, 0}, 0, 1, 497 }, 945 { GAS_ONLY|SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xEF, 0, 0}, 0, 1, 497 } 946 }; 947 948 static const x86_insn_info lea_insn[] = { 949 { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x8D, 0, 0}, 0, 2, 525 }, 950 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x8D, 0, 0}, 0, 2, 527 }, 951 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x8D, 0, 0}, 0, 2, 529 } 952 }; 953 954 static const x86_insn_info ldes_insn[] = { 955 { SUF_W|SUF_Z, NOT_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 16, 0, 0, 1, {0x00, 0, 0}, 0, 2, 525 }, 956 { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {MOD_Op0Add, 0, 0}, 32, 0, 0, 1, {0x00, 0, 0}, 0, 2, 527 } 957 }; 958 959 static const x86_insn_info lfgss_insn[] = { 960 { SUF_W|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 525 }, 961 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 527 }, 962 { SUF_Q|SUF_Z, ONLY_64, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 529 } 963 }; 964 965 static const x86_insn_info arith_insn[] = { 966 { SUF_B|SUF_Z, 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 1, {0x04, 0, 0}, 0, 2, 492 }, 967 { SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_Op2Add, MOD_Op1AddSp, 0}, 16, 0, 0, 2, {0x83, 0xC0, 0x05}, 0, 2, 569 }, 968 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op2Add, MOD_Op1AddSp, 0}, 32, 0, 0, 2, {0x83, 0xC0, 0x05}, 0, 2, 571 }, 969 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_Op2Add, MOD_Op1AddSp, 0}, 64, 0, 0, 2, {0x83, 0xC0, 0x05}, 0, 2, 573 }, 970 { SUF_B|SUF_Z, 0, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 0, 0, 0, 1, {0x80, 0, 0}, 0, 2, 415 }, 971 { SUF_B|SUF_Z, 0, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 0, 0, 0, 1, {0x80, 0, 0}, 0, 2, 407 }, 972 { SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 16, 0, 0, 1, {0x83, 0, 0}, 0, 2, 575 }, 973 { GAS_ILLEGAL|SUF_Z, 0, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 16, 0, 0, 1, {0x83, 0x81, 0}, 0, 2, 577 }, 974 { SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 16, 0, 0, 1, {0x83, 0x81, 0}, 0, 2, 579 }, 975 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 32, 0, 0, 1, {0x83, 0, 0}, 0, 2, 581 }, 976 { GAS_ILLEGAL|SUF_Z, NOT_64, CPU_386, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 32, 0, 0, 1, {0x83, 0x81, 0}, 0, 2, 583 }, 977 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 32, 0, 0, 1, {0x83, 0x81, 0}, 0, 2, 585 }, 978 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 64, 0, 0, 1, {0x83, 0, 0}, 0, 2, 587 }, 979 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 64, 0, 0, 1, {0x83, 0x81, 0}, 0, 2, 589 }, 980 { SUF_B|SUF_Z, 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 1, {0x00, 0, 0}, 0, 2, 317 }, 981 { SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 16, 0, 0, 1, {0x01, 0, 0}, 0, 2, 254 }, 982 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op0Add, 0, 0}, 32, 0, 0, 1, {0x01, 0, 0}, 0, 2, 260 }, 983 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 64, 0, 0, 1, {0x01, 0, 0}, 0, 2, 266 }, 984 { SUF_B|SUF_Z, 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 1, {0x02, 0, 0}, 0, 2, 319 }, 985 { SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 16, 0, 0, 1, {0x03, 0, 0}, 0, 2, 98 }, 986 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op0Add, 0, 0}, 32, 0, 0, 1, {0x03, 0, 0}, 0, 2, 101 }, 987 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 64, 0, 0, 1, {0x03, 0, 0}, 0, 2, 104 } 988 }; 989 990 static const x86_insn_info incdec_insn[] = { 991 { SUF_B|SUF_Z, 0, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 0, 0, 0, 1, {0xFE, 0, 0}, 0, 1, 415 }, 992 { SUF_W|SUF_Z, NOT_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 16, 0, 0, 1, {0x00, 0, 0}, 0, 1, 399 }, 993 { SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 16, 0, 0, 1, {0xFF, 0, 0}, 0, 1, 281 }, 994 { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {MOD_Op0Add, 0, 0}, 32, 0, 0, 1, {0x00, 0, 0}, 0, 1, 401 }, 995 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 32, 0, 0, 1, {0xFF, 0, 0}, 0, 1, 277 }, 996 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 64, 0, 0, 1, {0xFF, 0, 0}, 0, 1, 280 } 997 }; 998 999 static const x86_insn_info f6_insn[] = { 1000 { SUF_B|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xF6, 0, 0}, 0, 1, 415 }, 1001 { SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 16, 0, 0, 1, {0xF7, 0, 0}, 0, 1, 281 }, 1002 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0, 1, {0xF7, 0, 0}, 0, 1, 277 }, 1003 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_SpAdd, 0, 0}, 64, 0, 0, 1, {0xF7, 0, 0}, 0, 1, 280 } 1004 }; 1005 1006 static const x86_insn_info div_insn[] = { 1007 { SUF_B|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xF6, 0, 0}, 0, 1, 415 }, 1008 { SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 16, 0, 0, 1, {0xF7, 0, 0}, 0, 1, 281 }, 1009 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0, 1, {0xF7, 0, 0}, 0, 1, 277 }, 1010 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_SpAdd, 0, 0}, 64, 0, 0, 1, {0xF7, 0, 0}, 0, 1, 280 }, 1011 { SUF_B|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xF6, 0, 0}, 0, 2, 465 }, 1012 { SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 16, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 467 }, 1013 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 469 }, 1014 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_SpAdd, 0, 0}, 64, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 471 } 1015 }; 1016 1017 static const x86_insn_info test_insn[] = { 1018 { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xA8, 0, 0}, 0, 2, 492 }, 1019 { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xA9, 0, 0}, 0, 2, 619 }, 1020 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xA9, 0, 0}, 0, 2, 621 }, 1021 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xA9, 0, 0}, 0, 2, 623 }, 1022 { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xF6, 0, 0}, 0, 2, 415 }, 1023 { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xF6, 0, 0}, 0, 2, 407 }, 1024 { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 417 }, 1025 { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 409 }, 1026 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 419 }, 1027 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 411 }, 1028 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 421 }, 1029 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 413 }, 1030 { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x84, 0, 0}, 0, 2, 317 }, 1031 { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x85, 0, 0}, 0, 2, 254 }, 1032 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x85, 0, 0}, 0, 2, 260 }, 1033 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x85, 0, 0}, 0, 2, 266 }, 1034 { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x84, 0, 0}, 0, 2, 319 }, 1035 { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x85, 0, 0}, 0, 2, 98 }, 1036 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x85, 0, 0}, 0, 2, 101 }, 1037 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x85, 0, 0}, 0, 2, 104 } 1038 }; 1039 1040 static const x86_insn_info aadm_insn[] = { 1041 { SUF_Z, 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 2, {0xD4, 0x0A, 0}, 0, 0, 0 }, 1042 { SUF_Z, 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 1, {0xD4, 0, 0}, 0, 1, 3 } 1043 }; 1044 1045 static const x86_insn_info imul_insn[] = { 1046 { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xF6, 0, 0}, 5, 1, 415 }, 1047 { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xF7, 0, 0}, 5, 1, 281 }, 1048 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xF7, 0, 0}, 5, 1, 277 }, 1049 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xF7, 0, 0}, 5, 1, 280 }, 1050 { SUF_W|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 16, 0, 0, 2, {0x0F, 0xAF, 0}, 0, 2, 98 }, 1051 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0xAF, 0}, 0, 2, 101 }, 1052 { SUF_Q|SUF_Z, ONLY_64, CPU_386, 0, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0xAF, 0}, 0, 2, 104 }, 1053 { SUF_W|SUF_Z, 0, CPU_186, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x6B, 0, 0}, 0, 3, 98 }, 1054 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x6B, 0, 0}, 0, 3, 101 }, 1055 { SUF_Q|SUF_Z, ONLY_64, CPU_186, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x6B, 0, 0}, 0, 3, 104 }, 1056 { SUF_W|SUF_Z, 0, CPU_186, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x6B, 0, 0}, 0, 2, 297 }, 1057 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x6B, 0, 0}, 0, 2, 299 }, 1058 { SUF_Q|SUF_Z, ONLY_64, CPU_186, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x6B, 0, 0}, 0, 2, 301 }, 1059 { SUF_W|SUF_Z, 0, CPU_186, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x6B, 0x69, 0}, 0, 3, 107 }, 1060 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x6B, 0x69, 0}, 0, 3, 110 }, 1061 { SUF_Q|SUF_Z, ONLY_64, CPU_186, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x6B, 0x69, 0}, 0, 3, 113 }, 1062 { SUF_W|SUF_Z, 0, CPU_186, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x6B, 0x69, 0}, 0, 2, 303 }, 1063 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x6B, 0x69, 0}, 0, 2, 305 }, 1064 { SUF_Q|SUF_Z, ONLY_64, CPU_186, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x6B, 0x69, 0}, 0, 2, 307 } 1065 }; 1066 1067 static const x86_insn_info shift_insn[] = { 1068 { SUF_B|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xD2, 0, 0}, 0, 2, 545 }, 1069 { SUF_B|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xD0, 0, 0}, 0, 2, 547 }, 1070 { SUF_B|SUF_Z, 0, CPU_186, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xC0, 0, 0}, 0, 2, 415 }, 1071 { SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 16, 0, 0, 1, {0xD3, 0, 0}, 0, 2, 549 }, 1072 { SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 16, 0, 0, 1, {0xD1, 0, 0}, 0, 2, 551 }, 1073 { SUF_W|SUF_Z, 0, CPU_186, 0, 0, {MOD_SpAdd, 0, 0}, 16, 0, 0, 1, {0xC1, 0, 0}, 0, 2, 281 }, 1074 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0, 1, {0xD3, 0, 0}, 0, 2, 553 }, 1075 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0, 1, {0xD1, 0, 0}, 0, 2, 555 }, 1076 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0, 1, {0xC1, 0, 0}, 0, 2, 283 }, 1077 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_SpAdd, 0, 0}, 64, 0, 0, 1, {0xD3, 0, 0}, 0, 2, 557 }, 1078 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_SpAdd, 0, 0}, 64, 0, 0, 1, {0xD1, 0, 0}, 0, 2, 559 }, 1079 { SUF_Q|SUF_Z, ONLY_64, CPU_186, 0, 0, {MOD_SpAdd, 0, 0}, 64, 0, 0, 1, {0xC1, 0, 0}, 0, 2, 285 }, 1080 { GAS_ONLY|SUF_B|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xD0, 0, 0}, 0, 1, 415 }, 1081 { GAS_ONLY|SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 16, 0, 0, 1, {0xD1, 0, 0}, 0, 1, 281 }, 1082 { GAS_ONLY|SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0, 1, {0xD1, 0, 0}, 0, 1, 277 }, 1083 { GAS_ONLY|SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_SpAdd, 0, 0}, 64, 0, 0, 1, {0xD1, 0, 0}, 0, 1, 280 } 1084 }; 1085 1086 static const x86_insn_info shlrd_insn[] = { 1087 { SUF_W|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 2, {0x0F, 0x00, 0}, 0, 3, 254 }, 1088 { SUF_W|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 2, {0x0F, 0x01, 0}, 0, 3, 257 }, 1089 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 2, {0x0F, 0x00, 0}, 0, 3, 260 }, 1090 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 2, {0x0F, 0x01, 0}, 0, 3, 263 }, 1091 { SUF_Q|SUF_Z, ONLY_64, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 2, {0x0F, 0x00, 0}, 0, 3, 266 }, 1092 { SUF_Q|SUF_Z, ONLY_64, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 2, {0x0F, 0x01, 0}, 0, 3, 269 }, 1093 { GAS_ONLY|SUF_W|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 2, {0x0F, 0x01, 0}, 0, 2, 254 }, 1094 { GAS_ONLY|SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 2, {0x0F, 0x01, 0}, 0, 2, 260 }, 1095 { GAS_ONLY|SUF_Q|SUF_Z, ONLY_64, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 2, {0x0F, 0x01, 0}, 0, 2, 266 } 1096 }; 1097 1098 static const x86_insn_info call_insn[] = { 1099 { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, {0, 0, 0}, 0, 1, 669 }, 1100 { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, {0, 0, 0}, 0, 1, 670 }, 1101 { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, {0, 0, 0}, 0, 1, 671 }, 1102 { SUF_L|SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, {0, 0, 0}, 0, 1, 671 }, 1103 { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 1, {0xE8, 0, 0}, 0, 1, 672 }, 1104 { SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xE8, 0, 0}, 0, 1, 673 }, 1105 { SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 64, 0, 1, {0xE8, 0, 0}, 0, 1, 673 }, 1106 { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0xE8, 0, 0}, 0, 1, 674 }, 1107 { SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xFF, 0, 0}, 2, 1, 281 }, 1108 { SUF_L, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xFF, 0, 0}, 2, 1, 277 }, 1109 { SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 64, 0, 1, {0xFF, 0, 0}, 2, 1, 280 }, 1110 { GAS_ONLY|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0xFF, 0, 0}, 2, 1, 675 }, 1111 { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0xFF, 0, 0}, 2, 1, 668 }, 1112 { GAS_ILLEGAL|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 1, {0xFF, 0, 0}, 2, 1, 676 }, 1113 { GAS_ILLEGAL|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xFF, 0, 0}, 2, 1, 677 }, 1114 { GAS_ILLEGAL|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 64, 0, 1, {0xFF, 0, 0}, 2, 1, 678 }, 1115 { GAS_ILLEGAL|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0xFF, 0, 0}, 2, 1, 679 }, 1116 { GAS_ILLEGAL|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xFF, 0, 0}, 3, 1, 680 }, 1117 { GAS_ILLEGAL|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xFF, 0, 0}, 3, 1, 681 }, 1118 { GAS_ILLEGAL|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xFF, 0, 0}, 3, 1, 682 }, 1119 { GAS_ILLEGAL|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xFF, 0, 0}, 3, 1, 683 }, 1120 { GAS_ILLEGAL|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x9A, 0, 0}, 0, 1, 684 }, 1121 { GAS_ILLEGAL|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x9A, 0, 0}, 0, 1, 685 }, 1122 { GAS_ILLEGAL|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x9A, 0, 0}, 0, 1, 686 }, 1123 { GAS_ILLEGAL|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x9A, 0, 0}, 0, 1, 687 }, 1124 { GAS_ILLEGAL|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x9A, 0, 0}, 0, 1, 688 }, 1125 { GAS_ILLEGAL|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x9A, 0, 0}, 0, 1, 689 }, 1126 { GAS_ONLY|GAS_NO_REV|SUF_W, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x9A, 0, 0}, 0, 2, 563 }, 1127 { GAS_ONLY|GAS_NO_REV|SUF_L, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x9A, 0, 0}, 0, 2, 565 }, 1128 { GAS_ONLY|GAS_NO_REV|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x9A, 0, 0}, 0, 2, 567 } 1129 }; 1130 1131 static const x86_insn_info jmp_insn[] = { 1132 { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, {0, 0, 0}, 0, 1, 669 }, 1133 { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, {0, 0, 0}, 0, 1, 670 }, 1134 { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x00, 0, 0}, 0, 1, 671 }, 1135 { SUF_L|SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x00, 0, 0}, 0, 1, 671 }, 1136 { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0xEB, 0, 0}, 0, 1, 477 }, 1137 { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 1, {0xE9, 0, 0}, 0, 1, 672 }, 1138 { SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xE9, 0, 0}, 0, 1, 673 }, 1139 { SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 64, 0, 1, {0xE9, 0, 0}, 0, 1, 673 }, 1140 { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0xE9, 0, 0}, 0, 1, 674 }, 1141 { SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 1, {0xFF, 0, 0}, 4, 1, 281 }, 1142 { SUF_L, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xFF, 0, 0}, 4, 1, 277 }, 1143 { SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 64, 0, 1, {0xFF, 0, 0}, 4, 1, 280 }, 1144 { GAS_ONLY|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0xFF, 0, 0}, 4, 1, 675 }, 1145 { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0xFF, 0, 0}, 4, 1, 668 }, 1146 { GAS_ILLEGAL|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 1, {0xFF, 0, 0}, 4, 1, 676 }, 1147 { GAS_ILLEGAL|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xFF, 0, 0}, 4, 1, 677 }, 1148 { GAS_ILLEGAL|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 64, 0, 1, {0xFF, 0, 0}, 4, 1, 678 }, 1149 { GAS_ILLEGAL|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0xFF, 0, 0}, 4, 1, 679 }, 1150 { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xFF, 0, 0}, 5, 1, 680 }, 1151 { SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xFF, 0, 0}, 5, 1, 681 }, 1152 { SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xFF, 0, 0}, 5, 1, 682 }, 1153 { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xFF, 0, 0}, 5, 1, 683 }, 1154 { SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xEA, 0, 0}, 0, 1, 684 }, 1155 { SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xEA, 0, 0}, 0, 1, 685 }, 1156 { SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xEA, 0, 0}, 0, 1, 686 }, 1157 { GAS_ILLEGAL|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xEA, 0, 0}, 0, 1, 687 }, 1158 { GAS_ILLEGAL|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xEA, 0, 0}, 0, 1, 688 }, 1159 { GAS_ILLEGAL|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xEA, 0, 0}, 0, 1, 689 }, 1160 { GAS_ONLY|GAS_NO_REV|SUF_W, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xEA, 0, 0}, 0, 2, 563 }, 1161 { GAS_ONLY|GAS_NO_REV|SUF_L, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xEA, 0, 0}, 0, 2, 565 }, 1162 { GAS_ONLY|GAS_NO_REV|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xEA, 0, 0}, 0, 2, 567 } 1163 }; 1164 1165 static const x86_insn_info ljmpcall_insn[] = { 1166 { SUF_W, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 16, 0, 0, 1, {0xFF, 0, 0}, 0, 1, 34 }, 1167 { SUF_L, 0, CPU_386, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0, 1, {0xFF, 0, 0}, 0, 1, 58 }, 1168 { SUF_Q, ONLY_64, 0, 0, 0, {MOD_SpAdd, 0, 0}, 64, 0, 0, 1, {0xFF, 0, 0}, 0, 1, 6 }, 1169 { SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xFF, 0, 0}, 0, 1, 693 }, 1170 { GAS_NO_REV|SUF_W, NOT_64, 0, 0, 0, {MOD_Gap, MOD_Op0Add, 0}, 16, 0, 0, 1, {0x00, 0, 0}, 0, 2, 563 }, 1171 { GAS_NO_REV|SUF_L, NOT_64, CPU_386, 0, 0, {MOD_Gap, MOD_Op0Add, 0}, 32, 0, 0, 1, {0x00, 0, 0}, 0, 2, 565 }, 1172 { GAS_NO_REV|SUF_Z, NOT_64, 0, 0, 0, {MOD_Gap, MOD_Op0Add, 0}, 0, 0, 0, 1, {0x00, 0, 0}, 0, 2, 567 } 1173 }; 1174 1175 static const x86_insn_info retnf_insn[] = { 1176 { SUF_Z, NOT_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 1, {0x01, 0, 0}, 0, 0, 0 }, 1177 { SUF_Z, NOT_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 1, {0x00, 0, 0}, 0, 1, 400 }, 1178 { SUF_Z, ONLY_64, 0, 0, 0, {MOD_Op0Add, MOD_OpSizeR, 0}, 0, 0, 0, 1, {0x01, 0, 0}, 0, 0, 0 }, 1179 { SUF_Z, ONLY_64, 0, 0, 0, {MOD_Op0Add, MOD_OpSizeR, 0}, 0, 0, 0, 1, {0x00, 0, 0}, 0, 1, 400 }, 1180 { SUF_L|SUF_Q|SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_Op0Add, MOD_OpSizeR, 0}, 0, 0, 0, 1, {0x01, 0, 0}, 0, 0, 0 }, 1181 { SUF_L|SUF_Q|SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_Op0Add, MOD_OpSizeR, 0}, 0, 0, 0, 1, {0x00, 0, 0}, 0, 1, 400 } 1182 }; 1183 1184 static const x86_insn_info enter_insn[] = { 1185 { GAS_NO_REV|SUF_L|SUF_Z, NOT_64, CPU_186, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xC8, 0, 0}, 0, 2, 639 }, 1186 { GAS_NO_REV|SUF_Q|SUF_Z, ONLY_64, CPU_186, 0, 0, {0, 0, 0}, 64, 64, 0, 1, {0xC8, 0, 0}, 0, 2, 639 }, 1187 { GAS_ONLY|GAS_NO_REV|SUF_W|SUF_Z, 0, CPU_186, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xC8, 0, 0}, 0, 2, 639 } 1188 }; 1189 1190 static const x86_insn_info jcc_insn[] = { 1191 { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, {0, 0, 0}, 0, 1, 475 }, 1192 { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, {0, 0, 0}, 0, 1, 694 }, 1193 { SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, {0, 0, 0}, 0, 1, 695 }, 1194 { SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, {0, 0, 0}, 0, 1, 695 }, 1195 { SUF_Z, 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 64, 0, 1, {0x70, 0, 0}, 0, 1, 477 }, 1196 { SUF_Z, 0, CPU_186, 0, 0, {MOD_Op1Add, 0, 0}, 16, 64, 0, 2, {0x0F, 0x80, 0}, 0, 1, 672 }, 1197 { SUF_Z, NOT_64, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 2, {0x0F, 0x80, 0}, 0, 1, 673 }, 1198 { SUF_Z, ONLY_64, 0, 0, 0, {MOD_Op1Add, 0, 0}, 64, 64, 0, 2, {0x0F, 0x80, 0}, 0, 1, 673 }, 1199 { SUF_Z, 0, CPU_186, 0, 0, {MOD_Op1Add, 0, 0}, 0, 64, 0, 2, {0x0F, 0x80, 0}, 0, 1, 674 } 1200 }; 1201 1202 static const x86_insn_info jcxz_insn[] = { 1203 { SUF_Z, 0, 0, 0, 0, {MOD_AdSizeR, 0, 0}, 0, 0, 0, 0, {0, 0, 0}, 0, 1, 475 }, 1204 { SUF_Z, 0, 0, 0, 0, {MOD_AdSizeR, 0, 0}, 0, 64, 0, 1, {0xE3, 0, 0}, 0, 1, 477 } 1205 }; 1206 1207 static const x86_insn_info loop_insn[] = { 1208 { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, {0, 0, 0}, 0, 1, 475 }, 1209 { SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, {0, 0, 0}, 0, 2, 487 }, 1210 { SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 0, 64, 0, 0, {0, 0, 0}, 0, 2, 475 }, 1211 { SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 0, {0, 0, 0}, 0, 2, 483 }, 1212 { SUF_Z, NOT_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 1, {0xE0, 0, 0}, 0, 1, 477 }, 1213 { SUF_Z, 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 64, 0, 1, {0xE0, 0, 0}, 0, 2, 489 }, 1214 { SUF_Z, 0, CPU_386, 0, 0, {MOD_Op0Add, 0, 0}, 0, 64, 0, 1, {0xE0, 0, 0}, 0, 2, 477 }, 1215 { SUF_Z, ONLY_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 64, 0, 1, {0xE0, 0, 0}, 0, 2, 485 } 1216 }; 1217 1218 static const x86_insn_info loopw_insn[] = { 1219 { SUF_Z, NOT_64, 0, 0, 0, {MOD_Gap, MOD_AdSizeR, 0}, 0, 64, 0, 0, {0, 0, 0}, 0, 1, 475 }, 1220 { SUF_Z, NOT_64, 0, 0, 0, {MOD_Op0Add, MOD_AdSizeR, 0}, 0, 64, 0, 1, {0xE0, 0, 0}, 0, 1, 477 }, 1221 { SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 0, {0, 0, 0}, 0, 2, 487 }, 1222 { SUF_Z, NOT_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 64, 0, 1, {0xE0, 0, 0}, 0, 2, 489 } 1223 }; 1224 1225 static const x86_insn_info loopl_insn[] = { 1226 { SUF_Z, 0, 0, 0, 0, {MOD_Gap, MOD_AdSizeR, 0}, 0, 64, 0, 0, {0, 0, 0}, 0, 1, 475 }, 1227 { SUF_Z, 0, 0, 0, 0, {MOD_Op0Add, MOD_AdSizeR, 0}, 0, 64, 0, 1, {0xE0, 0, 0}, 0, 1, 477 }, 1228 { SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 0, 64, 0, 0, {0, 0, 0}, 0, 2, 475 }, 1229 { SUF_Z, 0, CPU_386, 0, 0, {MOD_Op0Add, 0, 0}, 0, 64, 0, 1, {0xE0, 0, 0}, 0, 2, 477 } 1230 }; 1231 1232 static const x86_insn_info loopq_insn[] = { 1233 { SUF_Z, ONLY_64, 0, 0, 0, {MOD_Gap, MOD_AdSizeR, 0}, 0, 64, 0, 0, {0, 0, 0}, 0, 1, 475 }, 1234 { SUF_Z, ONLY_64, 0, 0, 0, {MOD_Op0Add, MOD_AdSizeR, 0}, 0, 64, 0, 1, {0xE0, 0, 0}, 0, 1, 477 }, 1235 { SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 0, {0, 0, 0}, 0, 2, 483 }, 1236 { SUF_Z, ONLY_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 64, 0, 1, {0xE0, 0, 0}, 0, 2, 485 } 1237 }; 1238 1239 static const x86_insn_info setcc_insn[] = { 1240 { SUF_B|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0x0F, 0x90, 0}, 2, 1, 317 } 1241 }; 1242 1243 static const x86_insn_info cmpsd_insn[] = { 1244 { GAS_ILLEGAL|SUF_Z, NOT_AVX, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xA7, 0, 0}, 0, 0, 0 }, 1245 { SUF_Z, 0, CPU_SSE2, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0xF2, 2, {0x0F, 0xC2, 0}, 0, 3, 92 }, 1246 { SUF_Z, 0, CPU_SSE2, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0xF2, 2, {0x0F, 0xC2, 0}, 0, 3, 95 }, 1247 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC3, 2, {0x0F, 0xC2, 0}, 0, 4, 0 }, 1248 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC3, 2, {0x0F, 0xC2, 0}, 0, 4, 4 } 1249 }; 1250 1251 static const x86_insn_info movsd_insn[] = { 1252 { SUF_Z, NOT_AVX, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xA5, 0, 0}, 0, 0, 0 }, 1253 { SUF_Z, 0, CPU_SSE2, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0xF2, 2, {0x0F, 0x10, 0}, 0, 2, 92 }, 1254 { SUF_Z, 0, CPU_SSE2, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0xF2, 2, {0x0F, 0x10, 0}, 0, 2, 445 }, 1255 { SUF_Z, 0, CPU_SSE2, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0xF2, 2, {0x0F, 0x11, 0}, 0, 2, 47 }, 1256 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC3, 2, {0x0F, 0x10, 0}, 0, 3, 0 } 1257 }; 1258 1259 static const x86_insn_info bittest_insn[] = { 1260 { SUF_W|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 254 }, 1261 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 260 }, 1262 { SUF_Q|SUF_Z, ONLY_64, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 266 }, 1263 { SUF_W|SUF_Z, 0, CPU_386, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 16, 0, 0, 2, {0x0F, 0xBA, 0}, 0, 2, 281 }, 1264 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 32, 0, 0, 2, {0x0F, 0xBA, 0}, 0, 2, 283 }, 1265 { SUF_Q|SUF_Z, ONLY_64, CPU_386, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 64, 0, 0, 2, {0x0F, 0xBA, 0}, 0, 2, 285 } 1266 }; 1267 1268 static const x86_insn_info bsfr_insn[] = { 1269 { SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 98 }, 1270 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 101 }, 1271 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 104 } 1272 }; 1273 1274 static const x86_insn_info int_insn[] = { 1275 { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xCD, 0, 0}, 0, 1, 3 } 1276 }; 1277 1278 static const x86_insn_info bound_insn[] = { 1279 { SUF_W|SUF_Z, NOT_64, CPU_186, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x62, 0, 0}, 0, 2, 459 }, 1280 { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x62, 0, 0}, 0, 2, 353 } 1281 }; 1282 1283 static const x86_insn_info larlsl_insn[] = { 1284 { SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 449 }, 1285 { SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 98 }, 1286 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 451 }, 1287 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 453 }, 1288 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 455 }, 1289 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 457 } 1290 }; 1291 1292 static const x86_insn_info arpl_insn[] = { 1293 { SUF_W|SUF_Z, NOT_64, CPU_286, CPU_Prot, 0, {0, 0, 0}, 0, 0, 0, 1, {0x63, 0, 0}, 0, 2, 254 } 1294 }; 1295 1296 static const x86_insn_info str_insn[] = { 1297 { SUF_W|SUF_Z, 0, CPU_286, CPU_Prot, 0, {0, 0, 0}, 16, 0, 0, 2, {0x0F, 0x00, 0}, 1, 1, 389 }, 1298 { SUF_L|SUF_Z, 0, CPU_386, CPU_Prot, 0, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0x00, 0}, 1, 1, 26 }, 1299 { SUF_Q|SUF_Z, ONLY_64, CPU_286, CPU_Prot, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0x00, 0}, 1, 1, 30 }, 1300 { SUF_L|SUF_W|SUF_Z, 0, CPU_286, CPU_Prot, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 1, 1, 99 } 1301 }; 1302 1303 static const x86_insn_info prot286_insn[] = { 1304 { SUF_W|SUF_Z, 0, CPU_286, 0, 0, {MOD_SpAdd, MOD_Op1Add, 0}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 1, 99 } 1305 }; 1306 1307 static const x86_insn_info sldtmsw_insn[] = { 1308 { SUF_W|SUF_Z, 0, CPU_286, 0, 0, {MOD_SpAdd, MOD_Op1Add, 0}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 1, 34 }, 1309 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_SpAdd, MOD_Op1Add, 0}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 1, 58 }, 1310 { SUF_Q|SUF_Z, ONLY_64, CPU_286, 0, 0, {MOD_SpAdd, MOD_Op1Add, 0}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 1, 6 }, 1311 { SUF_W|SUF_Z, 0, CPU_286, 0, 0, {MOD_SpAdd, MOD_Op1Add, 0}, 16, 0, 0, 2, {0x0F, 0x00, 0}, 0, 1, 389 }, 1312 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_SpAdd, MOD_Op1Add, 0}, 32, 0, 0, 2, {0x0F, 0x00, 0}, 0, 1, 26 }, 1313 { SUF_Q|SUF_Z, ONLY_64, CPU_286, 0, 0, {MOD_SpAdd, MOD_Op1Add, 0}, 64, 0, 0, 2, {0x0F, 0x00, 0}, 0, 1, 30 } 1314 }; 1315 1316 static const x86_insn_info fld_insn[] = { 1317 { SUF_S|SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xD9, 0, 0}, 0, 1, 648 }, 1318 { SUF_L|SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xDD, 0, 0}, 0, 1, 212 }, 1319 { SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xDB, 0, 0}, 5, 1, 650 }, 1320 { SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0xD9, 0xC0, 0}, 0, 1, 322 } 1321 }; 1322 1323 static const x86_insn_info fstp_insn[] = { 1324 { SUF_S|SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xD9, 0, 0}, 3, 1, 648 }, 1325 { SUF_L|SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xDD, 0, 0}, 3, 1, 212 }, 1326 { SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xDB, 0, 0}, 7, 1, 650 }, 1327 { SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0xDD, 0xD8, 0}, 0, 1, 322 } 1328 }; 1329 1330 static const x86_insn_info fldstpt_insn[] = { 1331 { SUF_Z, 0, CPU_FPU, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xDB, 0, 0}, 0, 1, 562 } 1332 }; 1333 1334 static const x86_insn_info fildstp_insn[] = { 1335 { SUF_S|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xDF, 0, 0}, 0, 1, 647 }, 1336 { SUF_L|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xDB, 0, 0}, 0, 1, 648 }, 1337 { SUF_Q|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Gap, MOD_Op0Add, MOD_SpAdd}, 0, 0, 0, 1, {0xDD, 0, 0}, 0, 1, 212 }, 1338 { GAS_ONLY|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xDF, 0, 0}, 0, 1, 34 } 1339 }; 1340 1341 static const x86_insn_info fbldstp_insn[] = { 1342 { SUF_Z, 0, CPU_FPU, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xDF, 0, 0}, 0, 1, 562 } 1343 }; 1344 1345 static const x86_insn_info fst_insn[] = { 1346 { SUF_S|SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xD9, 0, 0}, 2, 1, 648 }, 1347 { SUF_L|SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xDD, 0, 0}, 2, 1, 212 }, 1348 { SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0xDD, 0xD0, 0}, 0, 1, 322 } 1349 }; 1350 1351 static const x86_insn_info fxch_insn[] = { 1352 { SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0xD9, 0xC8, 0}, 0, 1, 322 }, 1353 { SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0xD9, 0xC8, 0}, 0, 2, 321 }, 1354 { SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0xD9, 0xC8, 0}, 0, 2, 323 }, 1355 { SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0xD9, 0xC9, 0}, 0, 0, 0 } 1356 }; 1357 1358 static const x86_insn_info fcom_insn[] = { 1359 { SUF_S|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 0, 0, 0, 1, {0xD8, 0, 0}, 0, 1, 648 }, 1360 { SUF_L|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 0, 0, 0, 1, {0xDC, 0, 0}, 0, 1, 212 }, 1361 { SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0xD8, 0x00, 0}, 0, 1, 322 }, 1362 { GAS_ONLY|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 0, 0, 0, 1, {0xD8, 0, 0}, 0, 1, 58 }, 1363 { GAS_ONLY|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0xD8, 0x01, 0}, 0, 0, 0 }, 1364 { GAS_ILLEGAL|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0xD8, 0x00, 0}, 0, 2, 321 } 1365 }; 1366 1367 static const x86_insn_info fcom2_insn[] = { 1368 { SUF_Z, 0, CPU_286, CPU_FPU, 0, {MOD_Op0Add, MOD_Op1Add, 0}, 0, 0, 0, 2, {0x00, 0x00, 0}, 0, 1, 322 }, 1369 { SUF_Z, 0, CPU_286, CPU_FPU, 0, {MOD_Op0Add, MOD_Op1Add, 0}, 0, 0, 0, 2, {0x00, 0x00, 0}, 0, 2, 321 } 1370 }; 1371 1372 static const x86_insn_info farith_insn[] = { 1373 { SUF_S|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Gap, MOD_Gap, MOD_SpAdd}, 0, 0, 0, 1, {0xD8, 0, 0}, 0, 1, 648 }, 1374 { SUF_L|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Gap, MOD_Gap, MOD_SpAdd}, 0, 0, 0, 1, {0xDC, 0, 0}, 0, 1, 212 }, 1375 { SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Gap, MOD_Op1Add, 0}, 0, 0, 0, 2, {0xD8, 0x00, 0}, 0, 1, 322 }, 1376 { SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Gap, MOD_Op1Add, 0}, 0, 0, 0, 2, {0xD8, 0x00, 0}, 0, 2, 321 }, 1377 { SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0xDC, 0x00, 0}, 0, 1, 690 }, 1378 { GAS_ILLEGAL|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0xDC, 0x00, 0}, 0, 2, 323 }, 1379 { GAS_ONLY|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Gap, MOD_Op1Add, 0}, 0, 0, 0, 2, {0xDC, 0x00, 0}, 0, 2, 323 } 1380 }; 1381 1382 static const x86_insn_info farithp_insn[] = { 1383 { SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0xDE, 0x01, 0}, 0, 0, 0 }, 1384 { SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0xDE, 0x00, 0}, 0, 1, 322 }, 1385 { SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0xDE, 0x00, 0}, 0, 2, 323 } 1386 }; 1387 1388 static const x86_insn_info fiarith_insn[] = { 1389 { SUF_S|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_SpAdd, MOD_Op0Add, 0}, 0, 0, 0, 1, {0x04, 0, 0}, 0, 1, 647 }, 1390 { SUF_L|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_SpAdd, MOD_Op0Add, 0}, 0, 0, 0, 1, {0x00, 0, 0}, 0, 1, 648 } 1391 }; 1392 1393 static const x86_insn_info fldnstcw_insn[] = { 1394 { SUF_W|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xD9, 0, 0}, 0, 1, 34 } 1395 }; 1396 1397 static const x86_insn_info fstcw_insn[] = { 1398 { SUF_W|SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x9B, 0xD9, 0}, 7, 1, 34 } 1399 }; 1400 1401 static const x86_insn_info fnstsw_insn[] = { 1402 { SUF_W|SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xDD, 0, 0}, 7, 1, 34 }, 1403 { SUF_W|SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0xDF, 0xE0, 0}, 0, 1, 337 } 1404 }; 1405 1406 static const x86_insn_info fstsw_insn[] = { 1407 { SUF_W|SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x9B, 0xDD, 0}, 7, 1, 34 }, 1408 { SUF_W|SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 3, {0x9B, 0xDF, 0xE0}, 0, 1, 337 } 1409 }; 1410 1411 static const x86_insn_info ffree_insn[] = { 1412 { SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 2, {0x00, 0xC0, 0}, 0, 1, 322 } 1413 }; 1414 1415 static const x86_insn_info bswap_insn[] = { 1416 { SUF_L|SUF_Z, 0, CPU_486, 0, 0, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0xC8, 0}, 0, 1, 691 }, 1417 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0xC8, 0}, 0, 1, 692 } 1418 }; 1419 1420 static const x86_insn_info cmpxchgxadd_insn[] = { 1421 { SUF_B|SUF_Z, 0, CPU_486, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 317 }, 1422 { SUF_W|SUF_Z, 0, CPU_486, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 2, {0x0F, 0x01, 0}, 0, 2, 254 }, 1423 { SUF_L|SUF_Z, 0, CPU_486, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 2, {0x0F, 0x01, 0}, 0, 2, 260 }, 1424 { SUF_Q|SUF_Z, ONLY_64, CPU_486, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 2, {0x0F, 0x01, 0}, 0, 2, 266 } 1425 }; 1426 1427 static const x86_insn_info cmpxchg8b_insn[] = { 1428 { SUF_Q|SUF_Z, 0, CPU_586, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0xC7, 0}, 1, 1, 6 } 1429 }; 1430 1431 static const x86_insn_info cmovcc_insn[] = { 1432 { SUF_W|SUF_Z, 0, CPU_686, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 2, {0x0F, 0x40, 0}, 0, 2, 98 }, 1433 { SUF_L|SUF_Z, 0, CPU_686, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 2, {0x0F, 0x40, 0}, 0, 2, 101 }, 1434 { SUF_Q|SUF_Z, ONLY_64, CPU_686, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 2, {0x0F, 0x40, 0}, 0, 2, 104 } 1435 }; 1436 1437 static const x86_insn_info fcmovcc_insn[] = { 1438 { SUF_Z, 0, CPU_686, CPU_FPU, 0, {MOD_Op0Add, MOD_Op1Add, 0}, 0, 0, 0, 2, {0x00, 0x00, 0}, 0, 2, 321 } 1439 }; 1440 1441 static const x86_insn_info movnti_insn[] = { 1442 { SUF_L|SUF_Z, 0, CPU_P4, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0xC3, 0}, 0, 2, 331 }, 1443 { SUF_Q|SUF_Z, ONLY_64, CPU_P4, 0, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0xC3, 0}, 0, 2, 333 } 1444 }; 1445 1446 static const x86_insn_info clflush_insn[] = { 1447 { SUF_Z, 0, CPU_P3, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0xAE, 0}, 7, 1, 50 } 1448 }; 1449 1450 static const x86_insn_info movd_insn[] = { 1451 { SUF_Z, 0, CPU_386, CPU_MMX, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x6E, 0}, 0, 2, 287 }, 1452 { SUF_Z, ONLY_64, CPU_MMX, 0, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0x6E, 0}, 0, 2, 289 }, 1453 { SUF_Z, 0, CPU_386, CPU_MMX, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x7E, 0}, 0, 2, 288 }, 1454 { SUF_Z, ONLY_64, CPU_MMX, 0, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0x7E, 0}, 0, 2, 291 }, 1455 { SUF_Z, 0, CPU_386, CPU_SSE2, 0, {0, 0, 0}, 0, 0, 0x66, 2, {0x0F, 0x6E, 0}, 0, 2, 293 }, 1456 { SUF_Z, ONLY_64, CPU_SSE2, 0, 0, {0, 0, 0}, 64, 0, 0x66, 2, {0x0F, 0x6E, 0}, 0, 2, 295 }, 1457 { SUF_Z, 0, CPU_386, CPU_SSE2, 0, {0, 0, 0}, 0, 0, 0x66, 2, {0x0F, 0x7E, 0}, 0, 2, 188 }, 1458 { SUF_Z, ONLY_64, CPU_SSE2, 0, 0, {0, 0, 0}, 64, 0, 0x66, 2, {0x0F, 0x7E, 0}, 0, 2, 182 } 1459 }; 1460 1461 static const x86_insn_info movq_insn[] = { 1462 { GAS_ILLEGAL|SUF_Z, 0, CPU_MMX, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x6F, 0}, 0, 2, 140 }, 1463 { GAS_ILLEGAL|SUF_Z, ONLY_64, CPU_MMX, 0, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0x6E, 0}, 0, 2, 289 }, 1464 { GAS_ILLEGAL|SUF_Z, 0, CPU_MMX, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x7F, 0}, 0, 2, 325 }, 1465 { GAS_ILLEGAL|SUF_Z, ONLY_64, CPU_MMX, 0, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0x7E, 0}, 0, 2, 291 }, 1466 { GAS_ILLEGAL|SUF_Z, 0, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0xF3, 2, {0x0F, 0x7E, 0}, 0, 2, 64 }, 1467 { GAS_ILLEGAL|SUF_Z, 0, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0xF3, 2, {0x0F, 0x7E, 0}, 0, 2, 327 }, 1468 { GAS_ILLEGAL|SUF_Z, ONLY_64, CPU_SSE2, 0, 0, {0, 0, 0}, 64, 0, 0x66, 2, {0x0F, 0x6E, 0}, 0, 2, 295 }, 1469 { GAS_ILLEGAL|SUF_Z, 0, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0x66, 2, {0x0F, 0xD6, 0}, 0, 2, 329 }, 1470 { GAS_ILLEGAL|SUF_Z, ONLY_64, CPU_SSE2, 0, 0, {0, 0, 0}, 64, 0, 0x66, 2, {0x0F, 0x7E, 0}, 0, 2, 182 } 1471 }; 1472 1473 static const x86_insn_info mmxsse2_insn[] = { 1474 { SUF_Z, 0, CPU_MMX, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 140 }, 1475 { SUF_Z, 0, CPU_SSE2, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x66, 2, {0x0F, 0x00, 0}, 0, 2, 155 } 1476 }; 1477 1478 static const x86_insn_info pshift_insn[] = { 1479 { SUF_Z, 0, CPU_MMX, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 140 }, 1480 { SUF_Z, 0, CPU_MMX, 0, 0, {MOD_Gap, MOD_Op1Add, MOD_SpAdd}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 162 }, 1481 { SUF_Z, 0, CPU_SSE2, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x66, 2, {0x0F, 0x00, 0}, 0, 2, 155 }, 1482 { SUF_Z, 0, CPU_SSE2, 0, 0, {MOD_Gap, MOD_Op1Add, MOD_SpAdd}, 0, 0, 0x66, 2, {0x0F, 0x00, 0}, 0, 2, 2 } 1483 }; 1484 1485 static const x86_insn_info vpshift_insn[] = { 1486 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0xC1, 2, {0x0F, 0x00, 0}, 0, 2, 158 }, 1487 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Gap, MOD_Op1Add, MOD_SpAdd}, 0, 0, 0xC1, 2, {0x0F, 0x00, 0}, 0, 2, 505 }, 1488 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0xC1, 2, {0x0F, 0x00, 0}, 0, 3, 12 }, 1489 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Gap, MOD_Op1Add, MOD_SpAdd}, 0, 0, 0xC1, 2, {0x0F, 0x00, 0}, 0, 3, 1 }, 1490 { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0xC5, 2, {0x0F, 0x00, 0}, 0, 2, 633 }, 1491 { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_Gap, MOD_Op1Add, MOD_SpAdd}, 0, 0, 0xC5, 2, {0x0F, 0x00, 0}, 0, 2, 507 }, 1492 { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0xC5, 2, {0x0F, 0x00, 0}, 0, 3, 8 }, 1493 { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_Gap, MOD_Op1Add, MOD_SpAdd}, 0, 0, 0xC5, 2, {0x0F, 0x00, 0}, 0, 3, 200 } 1494 }; 1495 1496 static const x86_insn_info xmm_xmm128_256_insn[] = { 1497 { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 158 }, 1498 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 3, 12 }, 1499 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 2, {0x0F, 0x00, 0}, 0, 2, 197 }, 1500 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 2, {0x0F, 0x00, 0}, 0, 3, 16 } 1501 }; 1502 1503 static const x86_insn_info xmm_xmm128_256avx2_insn[] = { 1504 { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 158 }, 1505 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 3, 12 }, 1506 { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 2, {0x0F, 0x00, 0}, 0, 2, 197 }, 1507 { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 2, {0x0F, 0x00, 0}, 0, 3, 16 } 1508 }; 1509 1510 static const x86_insn_info xmm_xmm128_insn[] = { 1511 { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 158 }, 1512 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 3, 12 } 1513 }; 1514 1515 static const x86_insn_info cvt_rx_xmm32_insn[] = { 1516 { SUF_L|SUF_Z, 0, CPU_386, CPU_SSE, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 164 }, 1517 { SUF_L|SUF_Z, 0, CPU_386, CPU_SSE, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 353 }, 1518 { SUF_Q|SUF_Z, ONLY_64, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 64, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 170 }, 1519 { SUF_Q|SUF_Z, ONLY_64, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 64, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 355 } 1520 }; 1521 1522 static const x86_insn_info cvt_mm_xmm64_insn[] = { 1523 { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 309 }, 1524 { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 311 } 1525 }; 1526 1527 static const x86_insn_info cvt_xmm_mm_ps_insn[] = { 1528 { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 327 } 1529 }; 1530 1531 static const x86_insn_info cvt_xmm_rmx_insn[] = { 1532 { SUF_L|SUF_Z, 0, CPU_386, CPU_SSE, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 643 }, 1533 { SUF_L|SUF_Z, NOT_64, CPU_386, CPU_SSE, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 233 }, 1534 { SUF_Q|SUF_Z, ONLY_64, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 64, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 645 }, 1535 { SUF_L|SUF_Z, ONLY_AVX|NOT_64, CPU_386, CPU_AVX, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 3, 88 }, 1536 { SUF_L|SUF_Z, ONLY_AVX, CPU_386, CPU_AVX, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 3, 275 }, 1537 { SUF_Q|SUF_Z, ONLY_64|ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 64, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 3, 278 } 1538 }; 1539 1540 static const x86_insn_info xmm_xmm32_insn[] = { 1541 { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 92 }, 1542 { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 146 }, 1543 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 3, 0 }, 1544 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 3, 56 } 1545 }; 1546 1547 static const x86_insn_info ssecmp_128_insn[] = { 1548 { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_Imm8, MOD_PreAdd, MOD_SetVEX}, 0, 0, 0, 2, {0x0F, 0xC2, 0}, 0, 2, 158 }, 1549 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Imm8, MOD_PreAdd, 0}, 0, 0, 0xC0, 2, {0x0F, 0xC2, 0}, 0, 3, 12 }, 1550 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Imm8, MOD_PreAdd, 0}, 0, 0, 0xC4, 2, {0x0F, 0xC2, 0}, 0, 3, 16 } 1551 }; 1552 1553 static const x86_insn_info ssecmp_32_insn[] = { 1554 { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_Imm8, MOD_PreAdd, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0xC2, 0}, 0, 2, 92 }, 1555 { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_Imm8, MOD_PreAdd, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0xC2, 0}, 0, 2, 146 }, 1556 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Imm8, MOD_PreAdd, 0}, 0, 0, 0xC0, 2, {0x0F, 0xC2, 0}, 0, 3, 0 }, 1557 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Imm8, MOD_PreAdd, 0}, 0, 0, 0xC0, 2, {0x0F, 0xC2, 0}, 0, 3, 56 } 1558 }; 1559 1560 static const x86_insn_info xmm_xmm128_imm_insn[] = { 1561 { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 3, 185 } 1562 }; 1563 1564 static const x86_insn_info xmm_xmm128_imm_256avx2_insn[] = { 1565 { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 3, 185 }, 1566 { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 2, {0x0F, 0x00, 0}, 0, 3, 191 } 1567 }; 1568 1569 static const x86_insn_info xmm_xmm128_imm_256_insn[] = { 1570 { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 3, 158 }, 1571 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 4, 60 }, 1572 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 2, {0x0F, 0x00, 0}, 0, 4, 20 } 1573 }; 1574 1575 static const x86_insn_info xmm_xmm32_imm_insn[] = { 1576 { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 3, 92 }, 1577 { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 3, 146 }, 1578 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 4, 0 }, 1579 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 4, 56 } 1580 }; 1581 1582 static const x86_insn_info ldstmxcsr_insn[] = { 1583 { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_SpAdd, MOD_SetVEX, 0}, 0, 0, 0, 2, {0x0F, 0xAE, 0}, 0, 1, 58 } 1584 }; 1585 1586 static const x86_insn_info maskmovq_insn[] = { 1587 { SUF_Z, 0, CPU_MMX, CPU_P3, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0xF7, 0}, 0, 2, 635 } 1588 }; 1589 1590 static const x86_insn_info movau_insn[] = { 1591 { SUF_Z, NOT_AVX, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 155 }, 1592 { SUF_Z, NOT_AVX, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_Op1Add}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 479 }, 1593 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 2, 155 }, 1594 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_Op1Add}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 2, 479 }, 1595 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 2, {0x0F, 0x00, 0}, 0, 2, 191 }, 1596 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_Op1Add}, 0, 0, 0xC4, 2, {0x0F, 0x00, 0}, 0, 2, 481 } 1597 }; 1598 1599 static const x86_insn_info movhllhps_insn[] = { 1600 { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_Op1Add, MOD_SetVEX, 0}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 92 }, 1601 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 3, 0 } 1602 }; 1603 1604 static const x86_insn_info movhlp_insn[] = { 1605 { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 95 }, 1606 { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x01, 0}, 0, 2, 47 }, 1607 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 3, 4 } 1608 }; 1609 1610 static const x86_insn_info movmsk_insn[] = { 1611 { SUF_L|SUF_Z, 0, CPU_386, CPU_SSE, 0, {MOD_PreAdd, MOD_SetVEX, 0}, 0, 0, 0x00, 2, {0x0F, 0x50, 0}, 0, 2, 164 }, 1612 { SUF_Q|SUF_Z, ONLY_64, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_SetVEX, 0}, 64, 0, 0x00, 2, {0x0F, 0x50, 0}, 0, 2, 170 }, 1613 { SUF_L|SUF_Z, ONLY_AVX, CPU_386, CPU_AVX, 0, {MOD_PreAdd, 0, 0}, 0, 0, 0xC4, 2, {0x0F, 0x50, 0}, 0, 2, 313 }, 1614 { SUF_Q|SUF_Z, ONLY_64|ONLY_AVX, CPU_SSE, 0, 0, {MOD_PreAdd, 0, 0}, 64, 0, 0xC4, 2, {0x0F, 0x50, 0}, 0, 2, 315 } 1615 }; 1616 1617 static const x86_insn_info movnt_insn[] = { 1618 { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 595 }, 1619 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 2, {0x0F, 0x00, 0}, 0, 2, 597 } 1620 }; 1621 1622 static const x86_insn_info movntq_insn[] = { 1623 { SUF_Z, 0, CPU_SSE, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0xE7, 0}, 0, 2, 357 } 1624 }; 1625 1626 static const x86_insn_info movss_insn[] = { 1627 { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0xF3, 2, {0x0F, 0x10, 0}, 0, 2, 92 }, 1628 { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0xF3, 2, {0x0F, 0x10, 0}, 0, 2, 330 }, 1629 { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0xF3, 2, {0x0F, 0x11, 0}, 0, 2, 444 }, 1630 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC2, 2, {0x0F, 0x10, 0}, 0, 3, 0 } 1631 }; 1632 1633 static const x86_insn_info pextrw_insn[] = { 1634 { SUF_L|SUF_Z, NOT_AVX, CPU_MMX, CPU_P3, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0xC5, 0}, 0, 3, 161 }, 1635 { SUF_L|SUF_Z, 0, CPU_386, CPU_SSE2, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 2, {0x0F, 0xC5, 0}, 0, 3, 164 }, 1636 { SUF_Q|SUF_Z, ONLY_64|NOT_AVX, CPU_MMX, CPU_P3, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0xC5, 0}, 0, 3, 167 }, 1637 { SUF_Q|SUF_Z, ONLY_64, CPU_SSE2, 0, 0, {MOD_SetVEX, 0, 0}, 64, 0, 0x66, 2, {0x0F, 0xC5, 0}, 0, 3, 170 }, 1638 { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x15}, 0, 3, 173 }, 1639 { SUF_Z, 0, CPU_386, CPU_SSE41, 0, {MOD_SetVEX, 0, 0}, 32, 0, 0x66, 3, {0x0F, 0x3A, 0x15}, 0, 3, 176 }, 1640 { SUF_Z, ONLY_64, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 64, 0, 0x66, 3, {0x0F, 0x3A, 0x15}, 0, 3, 179 } 1641 }; 1642 1643 static const x86_insn_info pinsrw_insn[] = { 1644 { SUF_L|SUF_Z, NOT_AVX, CPU_MMX, CPU_P3, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0xC4, 0}, 0, 3, 116 }, 1645 { SUF_Q|SUF_Z, ONLY_64|NOT_AVX, CPU_MMX, CPU_P3, 0, {0, 0, 0}, 64, 64, 0, 2, {0x0F, 0xC4, 0}, 0, 3, 119 }, 1646 { SUF_L|SUF_Z, NOT_AVX, CPU_MMX, CPU_P3, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0xC4, 0}, 0, 3, 122 }, 1647 { SUF_L|SUF_Z, 0, CPU_386, CPU_SSE2, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 2, {0x0F, 0xC4, 0}, 0, 3, 125 }, 1648 { SUF_Q|SUF_Z, ONLY_64, CPU_SSE2, 0, 0, {MOD_SetVEX, 0, 0}, 64, 64, 0x66, 2, {0x0F, 0xC4, 0}, 0, 3, 128 }, 1649 { SUF_L|SUF_Z, 0, CPU_SSE2, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 2, {0x0F, 0xC4, 0}, 0, 3, 131 }, 1650 { SUF_L|SUF_Z, ONLY_AVX, CPU_386, CPU_AVX, 0, {0, 0, 0}, 0, 0, 0xC1, 2, {0x0F, 0xC4, 0}, 0, 4, 24 }, 1651 { SUF_Q|SUF_Z, ONLY_64|ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 64, 64, 0xC1, 2, {0x0F, 0xC4, 0}, 0, 4, 28 }, 1652 { SUF_L|SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC1, 2, {0x0F, 0xC4, 0}, 0, 4, 32 } 1653 }; 1654 1655 static const x86_insn_info pmovmskb_insn[] = { 1656 { SUF_L|SUF_Z, NOT_AVX, CPU_MMX, CPU_P3, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0xD7, 0}, 0, 2, 161 }, 1657 { SUF_L|SUF_Z, 0, CPU_386, CPU_SSE2, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 2, {0x0F, 0xD7, 0}, 0, 2, 164 }, 1658 { SUF_L|SUF_Z, ONLY_AVX, CPU_386, CPU_AVX2, 0, {0, 0, 0}, 0, 0, 0xC5, 2, {0x0F, 0xD7, 0}, 0, 2, 313 }, 1659 { SUF_Q|SUF_Z, ONLY_64|NOT_AVX, CPU_MMX, CPU_P3, 0, {0, 0, 0}, 64, 64, 0, 2, {0x0F, 0xD7, 0}, 0, 2, 167 }, 1660 { SUF_Q|SUF_Z, ONLY_64, CPU_SSE2, 0, 0, {MOD_SetVEX, 0, 0}, 64, 64, 0x66, 2, {0x0F, 0xD7, 0}, 0, 2, 170 }, 1661 { SUF_Q|SUF_Z, ONLY_64|ONLY_AVX, CPU_SSE2, 0, 0, {0, 0, 0}, 64, 64, 0xC5, 2, {0x0F, 0xD7, 0}, 0, 2, 315 } 1662 }; 1663 1664 static const x86_insn_info pshufw_insn[] = { 1665 { SUF_Z, 0, CPU_MMX, CPU_P3, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x70, 0}, 0, 3, 140 } 1666 }; 1667 1668 static const x86_insn_info xmm_xmm64_insn[] = { 1669 { SUF_Z, 0, CPU_SSE2, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 92 }, 1670 { SUF_Z, 0, CPU_SSE2, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 95 }, 1671 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 3, 0 }, 1672 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 3, 4 } 1673 }; 1674 1675 static const x86_insn_info ssecmp_64_insn[] = { 1676 { SUF_Z, 0, CPU_SSE2, 0, 0, {MOD_Imm8, MOD_PreAdd, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0xC2, 0}, 0, 2, 92 }, 1677 { SUF_Z, 0, CPU_SSE2, 0, 0, {MOD_Imm8, MOD_PreAdd, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0xC2, 0}, 0, 2, 95 }, 1678 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Imm8, MOD_PreAdd, 0}, 0, 0, 0xC0, 2, {0x0F, 0xC2, 0}, 0, 3, 0 }, 1679 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Imm8, MOD_PreAdd, 0}, 0, 0, 0xC0, 2, {0x0F, 0xC2, 0}, 0, 3, 4 } 1680 }; 1681 1682 static const x86_insn_info cvt_rx_xmm64_insn[] = { 1683 { SUF_L|SUF_Z, 0, CPU_386, CPU_SSE2, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 164 }, 1684 { SUF_L|SUF_Z, 0, CPU_386, CPU_SSE2, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 332 }, 1685 { SUF_Q|SUF_Z, ONLY_64, CPU_SSE2, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 64, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 170 }, 1686 { SUF_Q|SUF_Z, ONLY_64, CPU_SSE2, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 64, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 463 } 1687 }; 1688 1689 static const x86_insn_info cvt_mm_xmm_insn[] = { 1690 { SUF_Z, 0, CPU_SSE2, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 611 } 1691 }; 1692 1693 static const x86_insn_info cvt_xmm_mm_ss_insn[] = { 1694 { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 327 } 1695 }; 1696 1697 static const x86_insn_info eptvpid_insn[] = { 1698 { SUF_L|SUF_Z, NOT_64, CPU_386, CPU_EPTVPID, 0, {MOD_Op2Add, 0, 0}, 32, 0, 0x66, 3, {0x0F, 0x38, 0x80}, 0, 2, 607 }, 1699 { SUF_Q|SUF_Z, ONLY_64, CPU_EPTVPID, 0, 0, {MOD_Op2Add, 0, 0}, 64, 0, 0x66, 3, {0x0F, 0x38, 0x80}, 0, 2, 609 } 1700 }; 1701 1702 static const x86_insn_info vmxmemrd_insn[] = { 1703 { SUF_L|SUF_Z, NOT_64, CPU_P4, 0, 0, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0x78, 0}, 0, 2, 260 }, 1704 { SUF_Q|SUF_Z, ONLY_64, CPU_P4, 0, 0, {0, 0, 0}, 64, 64, 0, 2, {0x0F, 0x78, 0}, 0, 2, 266 } 1705 }; 1706 1707 static const x86_insn_info vmxmemwr_insn[] = { 1708 { SUF_L|SUF_Z, NOT_64, CPU_P4, 0, 0, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0x79, 0}, 0, 2, 101 }, 1709 { SUF_Q|SUF_Z, ONLY_64, CPU_P4, 0, 0, {0, 0, 0}, 64, 64, 0, 2, {0x0F, 0x79, 0}, 0, 2, 104 } 1710 }; 1711 1712 static const x86_insn_info vmxtwobytemem_insn[] = { 1713 { SUF_Z, 0, CPU_P4, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 2, {0x0F, 0xC7, 0}, 0, 1, 6 } 1714 }; 1715 1716 static const x86_insn_info vmxthreebytemem_insn[] = { 1717 { SUF_Z, 0, CPU_P4, 0, 0, {MOD_PreAdd, 0, 0}, 0, 0, 0x00, 2, {0x0F, 0xC7, 0}, 6, 1, 6 } 1718 }; 1719 1720 static const x86_insn_info maskmovdqu_insn[] = { 1721 { SUF_Z, 0, CPU_SSE2, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 2, {0x0F, 0xF7, 0}, 0, 2, 64 } 1722 }; 1723 1724 static const x86_insn_info movdq2q_insn[] = { 1725 { SUF_Z, 0, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0xF2, 2, {0x0F, 0xD6, 0}, 0, 2, 309 } 1726 }; 1727 1728 static const x86_insn_info movq2dq_insn[] = { 1729 { SUF_Z, 0, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0xF3, 2, {0x0F, 0xD6, 0}, 0, 2, 439 } 1730 }; 1731 1732 static const x86_insn_info pslrldq_insn[] = { 1733 { SUF_Z, 0, CPU_SSE2, 0, 0, {MOD_SpAdd, MOD_SetVEX, 0}, 0, 0, 0x66, 2, {0x0F, 0x73, 0}, 0, 2, 505 }, 1734 { SUF_Z, 0, CPU_SSE2, 0, 0, {MOD_SpAdd, MOD_SetVEX, 0}, 0, 0, 0x66, 2, {0x0F, 0x73, 0}, 0, 3, 1 }, 1735 { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0xC5, 2, {0x0F, 0x73, 0}, 0, 2, 507 }, 1736 { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0xC5, 2, {0x0F, 0x73, 0}, 0, 3, 200 } 1737 }; 1738 1739 static const x86_insn_info lddqu_insn[] = { 1740 { SUF_Z, 0, CPU_SSE3, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0xF2, 2, {0x0F, 0xF0, 0}, 0, 2, 591 }, 1741 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC7, 2, {0x0F, 0xF0, 0}, 0, 2, 593 } 1742 }; 1743 1744 static const x86_insn_info ssse3_insn[] = { 1745 { SUF_Z, NOT_AVX, CPU_SSSE3, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 3, {0x0F, 0x38, 0x00}, 0, 2, 140 }, 1746 { SUF_Z, 0, CPU_SSSE3, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x38, 0x00}, 0, 2, 158 }, 1747 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x38, 0x00}, 0, 3, 12 }, 1748 { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x00}, 0, 2, 197 }, 1749 { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x00}, 0, 3, 16 } 1750 }; 1751 1752 static const x86_insn_info ssse3imm_insn[] = { 1753 { SUF_Z, 0, CPU_SSSE3, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 3, {0x0F, 0x3A, 0x00}, 0, 3, 140 }, 1754 { SUF_Z, 0, CPU_SSSE3, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x00}, 0, 3, 185 } 1755 }; 1756 1757 static const x86_insn_info sse4_insn[] = { 1758 { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x38, 0x00}, 0, 2, 155 }, 1759 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x00}, 0, 2, 191 } 1760 }; 1761 1762 static const x86_insn_info sse4imm_256_insn[] = { 1763 { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x00}, 0, 3, 158 }, 1764 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 4, 60 }, 1765 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x3A, 0x00}, 0, 3, 197 }, 1766 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x3A, 0x00}, 0, 4, 20 } 1767 }; 1768 1769 static const x86_insn_info sse4imm_256avx2_insn[] = { 1770 { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x00}, 0, 3, 158 }, 1771 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 4, 60 }, 1772 { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x3A, 0x00}, 0, 3, 197 }, 1773 { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x3A, 0x00}, 0, 4, 20 } 1774 }; 1775 1776 static const x86_insn_info sse4imm_insn[] = { 1777 { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x00}, 0, 3, 158 }, 1778 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 4, 60 } 1779 }; 1780 1781 static const x86_insn_info sse4m32imm_insn[] = { 1782 { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x00}, 0, 3, 92 }, 1783 { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x00}, 0, 3, 146 }, 1784 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 4, 0 }, 1785 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 4, 56 } 1786 }; 1787 1788 static const x86_insn_info sse4m64imm_insn[] = { 1789 { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x00}, 0, 3, 92 }, 1790 { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x00}, 0, 3, 95 }, 1791 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 4, 0 }, 1792 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 4, 4 } 1793 }; 1794 1795 static const x86_insn_info sse4xmm0_insn[] = { 1796 { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x38, 0x00}, 0, 2, 155 }, 1797 { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x38, 0x00}, 0, 3, 236 } 1798 }; 1799 1800 static const x86_insn_info avx_sse4xmm0_insn[] = { 1801 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 4, 12 }, 1802 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x3A, 0x00}, 0, 4, 16 } 1803 }; 1804 1805 static const x86_insn_info avx2_sse4xmm0_insn[] = { 1806 { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 4, 12 }, 1807 { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x3A, 0x00}, 0, 4, 16 } 1808 }; 1809 1810 static const x86_insn_info crc32_insn[] = { 1811 { SUF_B|SUF_Z, 0, CPU_386, CPU_SSE42, 0, {0, 0, 0}, 0, 0, 0xF2, 3, {0x0F, 0x38, 0xF0}, 0, 2, 531 }, 1812 { SUF_W|SUF_Z, 0, CPU_386, CPU_SSE42, 0, {0, 0, 0}, 16, 0, 0xF2, 3, {0x0F, 0x38, 0xF1}, 0, 2, 533 }, 1813 { SUF_L|SUF_Z, 0, CPU_386, CPU_SSE42, 0, {0, 0, 0}, 32, 0, 0xF2, 3, {0x0F, 0x38, 0xF1}, 0, 2, 101 }, 1814 { SUF_B|SUF_Z, ONLY_64, CPU_SSE42, 0, 0, {0, 0, 0}, 64, 0, 0xF2, 3, {0x0F, 0x38, 0xF0}, 0, 2, 535 }, 1815 { SUF_Q|SUF_Z, ONLY_64, CPU_SSE42, 0, 0, {0, 0, 0}, 64, 0, 0xF2, 3, {0x0F, 0x38, 0xF1}, 0, 2, 104 } 1816 }; 1817 1818 static const x86_insn_info extractps_insn[] = { 1819 { SUF_Z, 0, CPU_386, CPU_SSE41, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x17}, 0, 3, 188 }, 1820 { SUF_Z, ONLY_64, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 64, 0, 0x66, 3, {0x0F, 0x3A, 0x17}, 0, 3, 179 } 1821 }; 1822 1823 static const x86_insn_info insertps_insn[] = { 1824 { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x21}, 0, 3, 146 }, 1825 { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x21}, 0, 3, 92 }, 1826 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x21}, 0, 4, 56 }, 1827 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x21}, 0, 4, 0 } 1828 }; 1829 1830 static const x86_insn_info movntdqa_insn[] = { 1831 { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x38, 0x2A}, 0, 2, 591 }, 1832 { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {0, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x2A}, 0, 2, 593 } 1833 }; 1834 1835 static const x86_insn_info sse4pcmpstr_insn[] = { 1836 { SUF_Z, 0, CPU_SSE42, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x00}, 0, 3, 185 } 1837 }; 1838 1839 static const x86_insn_info pextrb_insn[] = { 1840 { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x14}, 0, 3, 194 }, 1841 { SUF_Z, 0, CPU_386, CPU_SSE41, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x14}, 0, 3, 176 }, 1842 { SUF_Z, ONLY_64, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 64, 0, 0x66, 3, {0x0F, 0x3A, 0x14}, 0, 3, 179 } 1843 }; 1844 1845 static const x86_insn_info pextrd_insn[] = { 1846 { SUF_Z, 0, CPU_386, CPU_SSE41, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x16}, 0, 3, 188 } 1847 }; 1848 1849 static const x86_insn_info pextrq_insn[] = { 1850 { SUF_Z, ONLY_64, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 64, 0, 0x66, 3, {0x0F, 0x3A, 0x16}, 0, 3, 182 } 1851 }; 1852 1853 static const x86_insn_info pinsrb_insn[] = { 1854 { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x20}, 0, 3, 143 }, 1855 { SUF_Z, 0, CPU_386, CPU_SSE41, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x20}, 0, 3, 125 }, 1856 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x20}, 0, 4, 48 }, 1857 { SUF_Z, ONLY_AVX, CPU_386, CPU_AVX, 0, {0, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x20}, 0, 4, 52 } 1858 }; 1859 1860 static const x86_insn_info pinsrd_insn[] = { 1861 { SUF_Z, 0, CPU_386, CPU_SSE41, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x22}, 0, 3, 233 }, 1862 { SUF_Z, ONLY_AVX, CPU_386, CPU_AVX, 0, {0, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x22}, 0, 4, 88 } 1863 }; 1864 1865 static const x86_insn_info pinsrq_insn[] = { 1866 { SUF_Z, ONLY_64, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 64, 0, 0x66, 3, {0x0F, 0x3A, 0x22}, 0, 3, 227 }, 1867 { SUF_Z, ONLY_64|ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 64, 0, 0xC1, 3, {0x0F, 0x3A, 0x22}, 0, 4, 84 } 1868 }; 1869 1870 static const x86_insn_info sse4m16_insn[] = { 1871 { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x38, 0x00}, 0, 2, 441 }, 1872 { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x38, 0x00}, 0, 2, 64 }, 1873 { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x00}, 0, 2, 443 }, 1874 { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x00}, 0, 2, 208 } 1875 }; 1876 1877 static const x86_insn_info sse4m32_insn[] = { 1878 { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x38, 0x00}, 0, 2, 330 }, 1879 { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x38, 0x00}, 0, 2, 64 }, 1880 { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x00}, 0, 2, 473 }, 1881 { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x00}, 0, 2, 208 } 1882 }; 1883 1884 static const x86_insn_info sse4m64_insn[] = { 1885 { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x38, 0x00}, 0, 2, 445 }, 1886 { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x38, 0x00}, 0, 2, 64 }, 1887 { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x00}, 0, 2, 503 }, 1888 { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x00}, 0, 2, 208 } 1889 }; 1890 1891 static const x86_insn_info cnt_insn[] = { 1892 { SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0xF3, 2, {0x0F, 0x00, 0}, 0, 2, 98 }, 1893 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0xF3, 2, {0x0F, 0x00, 0}, 0, 2, 101 }, 1894 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0xF3, 2, {0x0F, 0x00, 0}, 0, 2, 104 } 1895 }; 1896 1897 static const x86_insn_info vmovd_insn[] = { 1898 { SUF_Z, ONLY_AVX, CPU_386, CPU_AVX, 0, {0, 0, 0}, 0, 0, 0xC1, 2, {0x0F, 0x6E, 0}, 0, 2, 293 }, 1899 { SUF_Z, ONLY_AVX, CPU_386, CPU_AVX, 0, {0, 0, 0}, 0, 0, 0xC1, 2, {0x0F, 0x7E, 0}, 0, 2, 188 } 1900 }; 1901 1902 static const x86_insn_info vmovq_insn[] = { 1903 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC2, 2, {0x0F, 0x7E, 0}, 0, 2, 64 }, 1904 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC2, 2, {0x0F, 0x7E, 0}, 0, 2, 445 }, 1905 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC1, 2, {0x0F, 0xD6, 0}, 0, 2, 47 }, 1906 { SUF_Z, ONLY_64|ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 64, 0, 0xC1, 2, {0x0F, 0x6E, 0}, 0, 2, 295 }, 1907 { SUF_Z, ONLY_64|ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 64, 0, 0xC1, 2, {0x0F, 0x7E, 0}, 0, 2, 182 } 1908 }; 1909 1910 static const x86_insn_info avx_xmm_xmm128_insn[] = { 1911 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 2, 155 }, 1912 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 2, {0x0F, 0x00, 0}, 0, 2, 191 } 1913 }; 1914 1915 static const x86_insn_info avx_sse4imm_insn[] = { 1916 { SUF_Z, ONLY_AVX, CPU_SSE41, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 3, 185 }, 1917 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 3, 185 }, 1918 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x3A, 0x00}, 0, 3, 191 } 1919 }; 1920 1921 static const x86_insn_info vmovddup_insn[] = { 1922 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 2, 64 }, 1923 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 2, 445 }, 1924 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 2, {0x0F, 0x00, 0}, 0, 2, 191 } 1925 }; 1926 1927 static const x86_insn_info avx_xmm_xmm64_insn[] = { 1928 { SUF_Z, ONLY_AVX, CPU_SSE2, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 2, 64 }, 1929 { SUF_Z, ONLY_AVX, CPU_SSE2, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 2, 445 } 1930 }; 1931 1932 static const x86_insn_info avx_xmm_xmm32_insn[] = { 1933 { SUF_Z, ONLY_AVX, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 2, 64 }, 1934 { SUF_Z, ONLY_AVX, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 2, 330 } 1935 }; 1936 1937 static const x86_insn_info avx_cvt_xmm64_insn[] = { 1938 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 2, 64 }, 1939 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 2, 445 }, 1940 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 2, {0x0F, 0x00, 0}, 0, 2, 447 } 1941 }; 1942 1943 static const x86_insn_info avx_ssse3_2op_insn[] = { 1944 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x38, 0x00}, 0, 2, 155 } 1945 }; 1946 1947 static const x86_insn_info avx2_ssse3_2op_insn[] = { 1948 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x38, 0x00}, 0, 2, 155 }, 1949 { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x00}, 0, 2, 191 } 1950 }; 1951 1952 static const x86_insn_info avx_cvt_xmm128_x_insn[] = { 1953 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 2, 155 } 1954 }; 1955 1956 static const x86_insn_info avx_cvt_xmm128_y_insn[] = { 1957 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 2, {0x0F, 0x00, 0}, 0, 2, 205 } 1958 }; 1959 1960 static const x86_insn_info avx_cvt_xmm128_insn[] = { 1961 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 2, 603 }, 1962 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 2, {0x0F, 0x00, 0}, 0, 2, 605 } 1963 }; 1964 1965 static const x86_insn_info vbroadcastss_insn[] = { 1966 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x38, 0x18}, 0, 2, 330 }, 1967 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x18}, 0, 2, 443 }, 1968 { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {0, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x38, 0x18}, 0, 2, 64 }, 1969 { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {0, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x18}, 0, 2, 208 } 1970 }; 1971 1972 static const x86_insn_info vbroadcastsd_insn[] = { 1973 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x19}, 0, 2, 473 }, 1974 { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {0, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x19}, 0, 2, 208 } 1975 }; 1976 1977 static const x86_insn_info vbroadcastif128_insn[] = { 1978 { SUF_Z, ONLY_AVX, 0, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x00}, 0, 2, 503 } 1979 }; 1980 1981 static const x86_insn_info vextractif128_insn[] = { 1982 { SUF_Z, ONLY_AVX, 0, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x3A, 0x00}, 0, 3, 230 } 1983 }; 1984 1985 static const x86_insn_info vinsertif128_insn[] = { 1986 { SUF_Z, ONLY_AVX, 0, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x3A, 0x00}, 0, 4, 8 } 1987 }; 1988 1989 static const x86_insn_info vzero_insn[] = { 1990 { SUF_Z, 0, CPU_AVX, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0, 2, {0x0F, 0x77, 0}, 0, 0, 0 } 1991 }; 1992 1993 static const x86_insn_info vmaskmov_insn[] = { 1994 { SUF_Z, ONLY_AVX, 0, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x38, 0x00}, 0, 3, 12 }, 1995 { SUF_Z, ONLY_AVX, 0, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x00}, 0, 3, 16 }, 1996 { SUF_Z, ONLY_AVX, 0, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x38, 0x02}, 0, 3, 203 }, 1997 { SUF_Z, ONLY_AVX, 0, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x02}, 0, 3, 206 } 1998 }; 1999 2000 static const x86_insn_info vpermil_insn[] = { 2001 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x38, 0x08}, 0, 3, 12 }, 2002 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x08}, 0, 3, 16 }, 2003 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 3, 185 }, 2004 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x3A, 0x00}, 0, 3, 191 } 2005 }; 2006 2007 static const x86_insn_info vperm2f128_insn[] = { 2008 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x3A, 0x06}, 0, 4, 20 } 2009 }; 2010 2011 static const x86_insn_info vperm_var_avx2_insn[] = { 2012 { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x00}, 0, 3, 16 } 2013 }; 2014 2015 static const x86_insn_info vperm_imm_avx2_insn[] = { 2016 { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xCD, 3, {0x0F, 0x3A, 0x00}, 0, 3, 191 } 2017 }; 2018 2019 static const x86_insn_info vperm2i128_avx2_insn[] = { 2020 { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {0, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x3A, 0x46}, 0, 4, 20 } 2021 }; 2022 2023 static const x86_insn_info vpbroadcastb_avx2_insn[] = { 2024 { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {0, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x38, 0x78}, 0, 2, 537 }, 2025 { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {0, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x78}, 0, 2, 539 }, 2026 { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {0, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x38, 0x78}, 0, 2, 629 }, 2027 { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {0, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x78}, 0, 2, 631 } 2028 }; 2029 2030 static const x86_insn_info vpbroadcastw_avx2_insn[] = { 2031 { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {0, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x38, 0x79}, 0, 2, 537 }, 2032 { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {0, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x79}, 0, 2, 539 }, 2033 { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {0, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x38, 0x79}, 0, 2, 541 }, 2034 { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {0, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x79}, 0, 2, 543 } 2035 }; 2036 2037 static const x86_insn_info vpbroadcastd_avx2_insn[] = { 2038 { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {0, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x38, 0x58}, 0, 2, 537 }, 2039 { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {0, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x58}, 0, 2, 539 }, 2040 { SUF_Z, ONLY_AVX, CPU_386, CPU_AVX2, 0, {0, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x38, 0x58}, 0, 2, 293 }, 2041 { SUF_Z, ONLY_AVX, CPU_386, CPU_AVX2, 0, {0, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x58}, 0, 2, 637 } 2042 }; 2043 2044 static const x86_insn_info vpbroadcastq_avx2_insn[] = { 2045 { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {0, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x38, 0x59}, 0, 2, 537 }, 2046 { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {0, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x59}, 0, 2, 539 }, 2047 { SUF_Z, ONLY_64|ONLY_AVX, CPU_AVX2, 0, 0, {0, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x38, 0x59}, 0, 2, 295 }, 2048 { SUF_Z, ONLY_64|ONLY_AVX, CPU_AVX2, 0, 0, {0, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x59}, 0, 2, 617 } 2049 }; 2050 2051 static const x86_insn_info vpshiftv_vexw0_avx2_insn[] = { 2052 { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x38, 0x00}, 0, 3, 12 }, 2053 { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x00}, 0, 3, 16 } 2054 }; 2055 2056 static const x86_insn_info vpshiftv_vexw1_avx2_insn[] = { 2057 { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC9, 3, {0x0F, 0x38, 0x00}, 0, 3, 12 }, 2058 { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xCD, 3, {0x0F, 0x38, 0x00}, 0, 3, 16 } 2059 }; 2060 2061 static const x86_insn_info vmaskmov_vexw1_avx2_insn[] = { 2062 { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC9, 3, {0x0F, 0x38, 0x00}, 0, 3, 12 }, 2063 { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xCD, 3, {0x0F, 0x38, 0x00}, 0, 3, 16 }, 2064 { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC9, 3, {0x0F, 0x38, 0x02}, 0, 3, 203 }, 2065 { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xCD, 3, {0x0F, 0x38, 0x02}, 0, 3, 206 } 2066 }; 2067 2068 static const x86_insn_info vex_66_0F3A_imm8_avx2_insn[] = { 2069 { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 4, 60 }, 2070 { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x3A, 0x00}, 0, 4, 20 } 2071 }; 2072 2073 static const x86_insn_info gather_64x_64x_insn[] = { 2074 { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC9, 3, {0x0F, 0x38, 0x00}, 0, 3, 221 }, 2075 { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xCD, 3, {0x0F, 0x38, 0x00}, 0, 3, 224 } 2076 }; 2077 2078 static const x86_insn_info gather_64x_64y_insn[] = { 2079 { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC9, 3, {0x0F, 0x38, 0x00}, 0, 3, 221 }, 2080 { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xCD, 3, {0x0F, 0x38, 0x00}, 0, 3, 272 } 2081 }; 2082 2083 static const x86_insn_info gather_32x_32y_insn[] = { 2084 { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x38, 0x00}, 0, 3, 239 }, 2085 { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x00}, 0, 3, 245 } 2086 }; 2087 2088 static const x86_insn_info gather_32x_32y_128_insn[] = { 2089 { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x38, 0x00}, 0, 3, 239 }, 2090 { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x00}, 0, 3, 242 } 2091 }; 2092 2093 static const x86_insn_info vfma_ps_insn[] = { 2094 { SUF_Z, ONLY_AVX, CPU_FMA, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x38, 0x00}, 0, 3, 12 }, 2095 { SUF_Z, ONLY_AVX, CPU_FMA, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x00}, 0, 3, 16 } 2096 }; 2097 2098 static const x86_insn_info vfma_pd_insn[] = { 2099 { SUF_Z, ONLY_AVX, CPU_FMA, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC9, 3, {0x0F, 0x38, 0x00}, 0, 3, 12 }, 2100 { SUF_Z, ONLY_AVX, CPU_FMA, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xCD, 3, {0x0F, 0x38, 0x00}, 0, 3, 16 } 2101 }; 2102 2103 static const x86_insn_info vfma_ss_insn[] = { 2104 { SUF_Z, ONLY_AVX, CPU_FMA, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x38, 0x00}, 0, 3, 0 }, 2105 { SUF_Z, ONLY_AVX, CPU_FMA, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x38, 0x00}, 0, 3, 56 } 2106 }; 2107 2108 static const x86_insn_info vfma_sd_insn[] = { 2109 { SUF_Z, ONLY_AVX, CPU_FMA, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC9, 3, {0x0F, 0x38, 0x00}, 0, 3, 0 }, 2110 { SUF_Z, ONLY_AVX, CPU_FMA, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC9, 3, {0x0F, 0x38, 0x00}, 0, 3, 4 } 2111 }; 2112 2113 static const x86_insn_info aes_insn[] = { 2114 { SUF_Z, 0, CPU_AES, 0, 0, {MOD_Op1Add, MOD_Op2Add, MOD_SetVEX}, 0, 0, 0x66, 3, {0x0F, 0x00, 0x00}, 0, 2, 158 }, 2115 { SUF_Z, ONLY_AVX, CPU_AES, CPU_AVX, 0, {MOD_Op1Add, MOD_Op2Add, 0}, 0, 0, 0xC1, 3, {0x0F, 0x00, 0x00}, 0, 3, 12 } 2116 }; 2117 2118 static const x86_insn_info aesimc_insn[] = { 2119 { SUF_Z, 0, CPU_AES, 0, 0, {MOD_Op1Add, MOD_Op2Add, MOD_SetVEX}, 0, 0, 0x66, 3, {0x0F, 0x00, 0x00}, 0, 2, 155 } 2120 }; 2121 2122 static const x86_insn_info aes_imm_insn[] = { 2123 { SUF_Z, 0, CPU_AES, 0, 0, {MOD_Op1Add, MOD_Op2Add, MOD_SetVEX}, 0, 0, 0x66, 3, {0x0F, 0x00, 0x00}, 0, 3, 185 } 2124 }; 2125 2126 static const x86_insn_info pclmulqdq_insn[] = { 2127 { SUF_Z, 0, CPU_CLMUL, 0, 0, {MOD_Op1Add, MOD_Op2Add, MOD_SetVEX}, 0, 0, 0x66, 3, {0x0F, 0x00, 0x00}, 0, 3, 158 }, 2128 { SUF_Z, ONLY_AVX, CPU_AVX, CPU_CLMUL, 0, {MOD_Op1Add, MOD_Op2Add, 0}, 0, 0, 0xC1, 3, {0x0F, 0x00, 0x00}, 0, 4, 60 } 2129 }; 2130 2131 static const x86_insn_info pclmulqdq_fixed_insn[] = { 2132 { SUF_Z, 0, CPU_CLMUL, 0, 0, {MOD_Imm8, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x44}, 0, 2, 158 }, 2133 { SUF_Z, ONLY_AVX, CPU_AVX, CPU_CLMUL, 0, {MOD_Imm8, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x44}, 0, 3, 12 } 2134 }; 2135 2136 static const x86_insn_info rdrand_insn[] = { 2137 { SUF_Z, 0, CPU_RDRAND, 0, 0, {0, 0, 0}, 16, 0, 0, 2, {0x0F, 0xC7, 0}, 6, 1, 389 }, 2138 { SUF_Z, 0, CPU_386, CPU_RDRAND, 0, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0xC7, 0}, 6, 1, 26 }, 2139 { SUF_Z, ONLY_64, CPU_RDRAND, 0, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0xC7, 0}, 6, 1, 30 } 2140 }; 2141 2142 static const x86_insn_info fs_gs_base_insn[] = { 2143 { SUF_Z, ONLY_64, CPU_FSGSBASE, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0xF3, 2, {0x0F, 0xAE, 0}, 0, 1, 26 }, 2144 { SUF_Z, ONLY_64, CPU_FSGSBASE, 0, 0, {MOD_SpAdd, 0, 0}, 64, 0, 0xF3, 2, {0x0F, 0xAE, 0}, 0, 1, 30 } 2145 }; 2146 2147 static const x86_insn_info avx_cvtps2ph_insn[] = { 2148 { SUF_Z, ONLY_AVX, CPU_AVX, CPU_F16C, 0, {MOD_PreAdd, MOD_Op2Add, 0}, 0, 0, 0xC0, 3, {0x0F, 0x3A, 0x00}, 0, 3, 209 }, 2149 { SUF_Z, ONLY_AVX, CPU_AVX, CPU_F16C, 0, {MOD_PreAdd, MOD_Op2Add, 0}, 0, 0, 0xC0, 3, {0x0F, 0x3A, 0x00}, 0, 3, 212 }, 2150 { SUF_Z, ONLY_AVX, CPU_AVX, CPU_F16C, 0, {MOD_PreAdd, MOD_Op2Add, 0}, 0, 0, 0xC4, 3, {0x0F, 0x3A, 0x00}, 0, 3, 215 }, 2151 { SUF_Z, ONLY_AVX, CPU_AVX, CPU_F16C, 0, {MOD_PreAdd, MOD_Op2Add, 0}, 0, 0, 0xC4, 3, {0x0F, 0x3A, 0x00}, 0, 3, 218 } 2152 }; 2153 2154 static const x86_insn_info avx_cvtph2ps_insn[] = { 2155 { SUF_Z, ONLY_AVX, CPU_AVX, CPU_F16C, 0, {MOD_PreAdd, MOD_Op2Add, 0}, 0, 0, 0xC0, 3, {0x0F, 0x38, 0x00}, 0, 2, 64 }, 2156 { SUF_Z, ONLY_AVX, CPU_AVX, CPU_F16C, 0, {MOD_PreAdd, MOD_Op2Add, 0}, 0, 0, 0xC0, 3, {0x0F, 0x38, 0x00}, 0, 2, 625 }, 2157 { SUF_Z, ONLY_AVX, CPU_AVX, CPU_F16C, 0, {MOD_PreAdd, MOD_Op2Add, 0}, 0, 0, 0xC4, 3, {0x0F, 0x38, 0x00}, 0, 2, 208 }, 2158 { SUF_Z, ONLY_AVX, CPU_AVX, CPU_F16C, 0, {MOD_PreAdd, MOD_Op2Add, 0}, 0, 0, 0xC4, 3, {0x0F, 0x38, 0x00}, 0, 2, 627 } 2159 }; 2160 2161 static const x86_insn_info extrq_insn[] = { 2162 { SUF_Z, 0, CPU_SSE4a, 0, 0, {0, 0, 0}, 0, 0, 0x66, 2, {0x0F, 0x78, 0}, 0, 3, 65 }, 2163 { SUF_Z, 0, CPU_SSE4a, 0, 0, {0, 0, 0}, 0, 0, 0x66, 2, {0x0F, 0x79, 0}, 0, 2, 64 } 2164 }; 2165 2166 static const x86_insn_info insertq_insn[] = { 2167 { SUF_Z, 0, CPU_SSE4a, 0, 0, {0, 0, 0}, 0, 0, 0xF2, 2, {0x0F, 0x78, 0}, 0, 4, 64 }, 2168 { SUF_Z, 0, CPU_SSE4a, 0, 0, {0, 0, 0}, 0, 0, 0xF2, 2, {0x0F, 0x79, 0}, 0, 2, 64 } 2169 }; 2170 2171 static const x86_insn_info movntsd_insn[] = { 2172 { SUF_Z, 0, CPU_SSE4a, 0, 0, {0, 0, 0}, 0, 0, 0xF2, 2, {0x0F, 0x2B, 0}, 0, 2, 47 } 2173 }; 2174 2175 static const x86_insn_info movntss_insn[] = { 2176 { SUF_Z, 0, CPU_SSE4a, 0, 0, {0, 0, 0}, 0, 0, 0xF3, 2, {0x0F, 0x2B, 0}, 0, 2, 444 } 2177 }; 2178 2179 static const x86_insn_info vfrc_pdps_insn[] = { 2180 { SUF_Z, 0, CPU_XOP, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x80, 2, {0x09, 0x80, 0}, 0, 2, 155 }, 2181 { SUF_Z, 0, CPU_XOP, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x84, 2, {0x09, 0x80, 0}, 0, 2, 191 } 2182 }; 2183 2184 static const x86_insn_info vfrczsd_insn[] = { 2185 { SUF_Z, 0, CPU_XOP, 0, 0, {0, 0, 0}, 0, 0, 0x80, 2, {0x09, 0x83, 0}, 0, 2, 64 }, 2186 { SUF_Z, 0, CPU_XOP, 0, 0, {0, 0, 0}, 0, 0, 0x80, 2, {0x09, 0x83, 0}, 0, 2, 445 } 2187 }; 2188 2189 static const x86_insn_info vfrczss_insn[] = { 2190 { SUF_Z, 0, CPU_XOP, 0, 0, {0, 0, 0}, 0, 0, 0x80, 2, {0x09, 0x82, 0}, 0, 2, 64 }, 2191 { SUF_Z, 0, CPU_XOP, 0, 0, {0, 0, 0}, 0, 0, 0x80, 2, {0x09, 0x82, 0}, 0, 2, 330 } 2192 }; 2193 2194 static const x86_insn_info vpcmov_insn[] = { 2195 { SUF_Z, 0, CPU_XOP, 0, 0, {0, 0, 0}, 0, 0, 0x80, 2, {0x08, 0xA2, 0}, 0, 4, 12 }, 2196 { SUF_Z, 0, CPU_XOP, 0, 0, {0, 0, 0}, 0, 0, 0x88, 2, {0x08, 0xA2, 0}, 0, 4, 68 }, 2197 { SUF_Z, 0, CPU_XOP, 0, 0, {0, 0, 0}, 0, 0, 0x84, 2, {0x08, 0xA2, 0}, 0, 4, 16 }, 2198 { SUF_Z, 0, CPU_XOP, 0, 0, {0, 0, 0}, 0, 0, 0x8C, 2, {0x08, 0xA2, 0}, 0, 4, 72 } 2199 }; 2200 2201 static const x86_insn_info vpcom_insn[] = { 2202 { SUF_Z, 0, CPU_XOP, 0, 0, {MOD_Op1Add, MOD_Imm8, 0}, 0, 0, 0x80, 2, {0x08, 0x00, 0}, 0, 3, 12 } 2203 }; 2204 2205 static const x86_insn_info vpcom_imm_insn[] = { 2206 { SUF_Z, 0, CPU_XOP, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x80, 2, {0x08, 0x00, 0}, 0, 4, 60 } 2207 }; 2208 2209 static const x86_insn_info vphaddsub_insn[] = { 2210 { SUF_Z, 0, CPU_XOP, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x80, 2, {0x09, 0x00, 0}, 0, 2, 155 } 2211 }; 2212 2213 static const x86_insn_info vpma_insn[] = { 2214 { SUF_Z, 0, CPU_XOP, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x80, 2, {0x08, 0x00, 0}, 0, 4, 12 } 2215 }; 2216 2217 static const x86_insn_info vpperm_insn[] = { 2218 { SUF_Z, 0, CPU_XOP, 0, 0, {0, 0, 0}, 0, 0, 0x80, 2, {0x08, 0xA3, 0}, 0, 4, 12 }, 2219 { SUF_Z, 0, CPU_XOP, 0, 0, {0, 0, 0}, 0, 0, 0x88, 2, {0x08, 0xA3, 0}, 0, 4, 68 } 2220 }; 2221 2222 static const x86_insn_info vprot_insn[] = { 2223 { SUF_Z, 0, CPU_XOP, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x80, 2, {0x09, 0x90, 0}, 0, 3, 155 }, 2224 { SUF_Z, 0, CPU_XOP, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x88, 2, {0x09, 0x90, 0}, 0, 3, 12 }, 2225 { SUF_Z, 0, CPU_XOP, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x80, 2, {0x08, 0xC0, 0}, 0, 3, 185 } 2226 }; 2227 2228 static const x86_insn_info amd_vpshift_insn[] = { 2229 { SUF_Z, 0, CPU_XOP, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x80, 2, {0x09, 0x00, 0}, 0, 3, 155 }, 2230 { SUF_Z, 0, CPU_XOP, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x88, 2, {0x09, 0x00, 0}, 0, 3, 12 } 2231 }; 2232 2233 static const x86_insn_info fma_128_256_insn[] = { 2234 { SUF_Z, ONLY_AVX, CPU_FMA4, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 4, 12 }, 2235 { SUF_Z, ONLY_AVX, CPU_FMA4, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC9, 3, {0x0F, 0x3A, 0x00}, 0, 4, 68 }, 2236 { SUF_Z, ONLY_AVX, CPU_FMA4, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x3A, 0x00}, 0, 4, 16 }, 2237 { SUF_Z, ONLY_AVX, CPU_FMA4, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xCD, 3, {0x0F, 0x3A, 0x00}, 0, 4, 72 } 2238 }; 2239 2240 static const x86_insn_info fma_128_m32_insn[] = { 2241 { SUF_Z, ONLY_AVX, CPU_FMA4, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 4, 36 }, 2242 { SUF_Z, ONLY_AVX, CPU_FMA4, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 4, 76 }, 2243 { SUF_Z, ONLY_AVX, CPU_FMA4, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC9, 3, {0x0F, 0x3A, 0x00}, 0, 4, 80 } 2244 }; 2245 2246 static const x86_insn_info fma_128_m64_insn[] = { 2247 { SUF_Z, ONLY_AVX, CPU_FMA4, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 4, 36 }, 2248 { SUF_Z, ONLY_AVX, CPU_FMA4, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 4, 40 }, 2249 { SUF_Z, ONLY_AVX, CPU_FMA4, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC9, 3, {0x0F, 0x3A, 0x00}, 0, 4, 44 } 2250 }; 2251 2252 static const x86_insn_info xsaveopt64_insn[] = { 2253 { SUF_Z, ONLY_64, 0, 0, 0, {MOD_SpAdd, MOD_Op0Add, MOD_Op1Add}, 64, 0, 0, 2, {0x00, 0x00, 0}, 0, 1, 526 } 2254 }; 2255 2256 static const x86_insn_info movbe_insn[] = { 2257 { SUF_Z, 0, CPU_MOVBE, 0, 0, {0, 0, 0}, 16, 0, 0, 3, {0x0F, 0x38, 0xF0}, 0, 2, 459 }, 2258 { SUF_Z, 0, CPU_MOVBE, 0, 0, {0, 0, 0}, 16, 0, 0, 3, {0x0F, 0x38, 0xF1}, 0, 2, 461 }, 2259 { SUF_Z, 0, CPU_386, CPU_MOVBE, 0, {0, 0, 0}, 32, 0, 0, 3, {0x0F, 0x38, 0xF0}, 0, 2, 353 }, 2260 { SUF_Z, 0, CPU_386, CPU_MOVBE, 0, {0, 0, 0}, 32, 0, 0, 3, {0x0F, 0x38, 0xF1}, 0, 2, 331 }, 2261 { SUF_Z, ONLY_64, CPU_MOVBE, 0, 0, {0, 0, 0}, 64, 0, 0, 3, {0x0F, 0x38, 0xF0}, 0, 2, 463 }, 2262 { SUF_Z, ONLY_64, CPU_MOVBE, 0, 0, {0, 0, 0}, 64, 0, 0, 3, {0x0F, 0x38, 0xF1}, 0, 2, 333 } 2263 }; 2264 2265 static const x86_insn_info vex_gpr_ndd_rm_0F38_regext_insn[] = { 2266 { SUF_W|SUF_Z, ONLY_AVX, CPU_386, 0, 0, {MOD_PreAdd, MOD_Op2Add, MOD_SpAdd}, 32, 0, 0xC0, 3, {0x0F, 0x38, 0x00}, 0, 2, 249 }, 2267 { SUF_L|SUF_Z, ONLY_64|ONLY_AVX, 0, 0, 0, {MOD_PreAdd, MOD_Op2Add, MOD_SpAdd}, 64, 0, 0xC0, 3, {0x0F, 0x38, 0x00}, 0, 2, 252 } 2268 }; 2269 2270 static const x86_insn_info vex_gpr_reg_rm_0F_imm8_insn[] = { 2271 { SUF_W|SUF_Z, ONLY_AVX, CPU_386, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_Op2Add}, 32, 0, 0xC0, 3, {0x0F, 0x00, 0x00}, 0, 3, 134 }, 2272 { SUF_L|SUF_Z, ONLY_64|ONLY_AVX, 0, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_Op2Add}, 64, 0, 0xC0, 3, {0x0F, 0x00, 0x00}, 0, 3, 137 } 2273 }; 2274 2275 static const x86_insn_info vex_gpr_reg_nds_rm_0F_insn[] = { 2276 { SUF_L|SUF_Z, ONLY_AVX, CPU_386, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_Op2Add}, 32, 0, 0xC0, 3, {0x0F, 0x00, 0x00}, 0, 3, 248 }, 2277 { SUF_Q|SUF_Z, ONLY_64|ONLY_AVX, 0, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_Op2Add}, 64, 0, 0xC0, 3, {0x0F, 0x00, 0x00}, 0, 3, 251 } 2278 }; 2279 2280 static const x86_insn_info vex_gpr_reg_rm_nds_0F_insn[] = { 2281 { SUF_L|SUF_Z, ONLY_AVX, CPU_386, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_Op2Add}, 32, 0, 0xC0, 3, {0x0F, 0x00, 0x00}, 0, 3, 149 }, 2282 { SUF_Q|SUF_Z, ONLY_64|ONLY_AVX, 0, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_Op2Add}, 64, 0, 0xC0, 3, {0x0F, 0x00, 0x00}, 0, 3, 152 } 2283 }; 2284 2285 static const x86_insn_info invpcid_insn[] = { 2286 { SUF_Z, NOT_64, CPU_386, CPU_INVPCID, CPU_Priv, {0, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x38, 0x82}, 0, 2, 607 }, 2287 { SUF_Z, ONLY_64, CPU_INVPCID, CPU_Priv, 0, {0, 0, 0}, 0, 64, 0x66, 3, {0x0F, 0x38, 0x82}, 0, 2, 609 } 2288 }; 2289 2290 static const x86_insn_info now3d_insn[] = { 2291 { SUF_Z, 0, CPU_3DNow, 0, 0, {MOD_Imm8, 0, 0}, 0, 0, 0, 2, {0x0F, 0x0F, 0}, 0, 2, 140 } 2292 }; 2293 2294 static const x86_insn_info cmpxchg16b_insn[] = { 2295 { SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0xC7, 0}, 1, 1, 504 } 2296 }; 2297 2298 static const x86_insn_info invlpga_insn[] = { 2299 { SUF_Z, 0, CPU_SVM, 0, 0, {0, 0, 0}, 0, 0, 0, 3, {0x0F, 0x01, 0xDF}, 0, 0, 0 }, 2300 { SUF_Z, 0, CPU_386, CPU_SVM, 0, {0, 0, 0}, 0, 0, 0, 3, {0x0F, 0x01, 0xDF}, 0, 2, 509 } 2301 }; 2302 2303 static const x86_insn_info skinit_insn[] = { 2304 { SUF_Z, 0, CPU_SVM, 0, 0, {0, 0, 0}, 0, 0, 0, 3, {0x0F, 0x01, 0xDE}, 0, 0, 0 }, 2305 { SUF_Z, 0, CPU_SVM, 0, 0, {0, 0, 0}, 0, 0, 0, 3, {0x0F, 0x01, 0xDE}, 0, 1, 649 } 2306 }; 2307 2308 static const x86_insn_info svm_rax_insn[] = { 2309 { SUF_Z, 0, CPU_SVM, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 3, {0x0F, 0x01, 0x00}, 0, 0, 0 }, 2310 { SUF_Z, 0, CPU_SVM, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 3, {0x0F, 0x01, 0x00}, 0, 1, 509 } 2311 }; 2312 2313 static const x86_insn_info padlock_insn[] = { 2314 { SUF_Z, 0, CPU_PadLock, 0, 0, {MOD_Imm8, MOD_PreAdd, MOD_Op1Add}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 0, 0 } 2315 }; 2316 2317 static const x86_insn_info cyrixmmx_insn[] = { 2318 { SUF_Z, 0, CPU_Cyrix, CPU_MMX, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 140 } 2319 }; 2320 2321 static const x86_insn_info pmachriw_insn[] = { 2322 { SUF_Z, 0, CPU_Cyrix, CPU_MMX, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x5E, 0}, 0, 2, 311 } 2323 }; 2324 2325 static const x86_insn_info rdwrshr_insn[] = { 2326 { SUF_Z, 0, CPU_686, CPU_Cyrix, CPU_SMM, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0x0F, 0x36, 0}, 0, 1, 90 } 2327 }; 2328 2329 static const x86_insn_info rsdc_insn[] = { 2330 { SUF_Z, 0, CPU_486, CPU_Cyrix, CPU_SMM, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x79, 0}, 0, 2, 561 } 2331 }; 2332 2333 static const x86_insn_info cyrixsmm_insn[] = { 2334 { SUF_Z, 0, CPU_486, CPU_Cyrix, CPU_SMM, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 1, 562 } 2335 }; 2336 2337 static const x86_insn_info svdc_insn[] = { 2338 { SUF_Z, 0, CPU_486, CPU_Cyrix, CPU_SMM, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x78, 0}, 0, 2, 615 } 2339 }; 2340 2341 static const x86_insn_info ibts_insn[] = { 2342 { SUF_Z, 0, CPU_386, CPU_Obs, CPU_Undoc, {0, 0, 0}, 16, 0, 0, 2, {0x0F, 0xA7, 0}, 0, 2, 254 }, 2343 { SUF_Z, 0, CPU_386, CPU_Obs, CPU_Undoc, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0xA7, 0}, 0, 2, 260 } 2344 }; 2345 2346 static const x86_insn_info umov_insn[] = { 2347 { SUF_Z, 0, CPU_386, CPU_Undoc, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x10, 0}, 0, 2, 317 }, 2348 { SUF_Z, 0, CPU_386, CPU_Undoc, 0, {0, 0, 0}, 16, 0, 0, 2, {0x0F, 0x11, 0}, 0, 2, 254 }, 2349 { SUF_Z, 0, CPU_386, CPU_Undoc, 0, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0x11, 0}, 0, 2, 260 }, 2350 { SUF_Z, 0, CPU_386, CPU_Undoc, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x12, 0}, 0, 2, 319 }, 2351 { SUF_Z, 0, CPU_386, CPU_Undoc, 0, {0, 0, 0}, 16, 0, 0, 2, {0x0F, 0x13, 0}, 0, 2, 98 }, 2352 { SUF_Z, 0, CPU_386, CPU_Undoc, 0, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0x13, 0}, 0, 2, 101 } 2353 }; 2354 2355 static const x86_insn_info xbts_insn[] = { 2356 { SUF_Z, 0, CPU_386, CPU_Obs, CPU_Undoc, {0, 0, 0}, 16, 0, 0, 2, {0x0F, 0xA6, 0}, 0, 2, 459 }, 2357 { SUF_Z, 0, CPU_386, CPU_Obs, CPU_Undoc, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0xA6, 0}, 0, 2, 353 } 2358 }; 2359 2360
