HomeSort by relevance Sort by last modified time
    Searched defs:reg0 (Results 1 - 7 of 7) sorted by null

  /dalvik/vm/compiler/codegen/arm/Thumb/
Gen.cpp 219 int reg0 = loadValue(cUnit, rlSrc, kCoreReg).lowReg; local
222 newLIR2(cUnit, kThumbAndRR, reg0, signMask);
224 storeWordDisp(cUnit, r6SELF, offset, reg0);
226 dvmCompilerClobber(cUnit, reg0);
254 int reg0 = loadValue(cUnit, rlSrc1, kCoreReg).lowReg; local
256 newLIR2(cUnit, kThumbCmpRR, reg0, reg1);
259 newLIR2(cUnit, kThumbMovRR, reg0, reg1);
262 newLIR3(cUnit, kThumbStrRRI5, reg0, r6SELF, offset >> 2);
265 dvmCompilerClobber(cUnit,reg0);
  /dalvik/vm/compiler/codegen/mips/Mips32/
Gen.cpp 250 int reg0 = loadValue(cUnit, rlSrc, kCoreReg).lowReg; local
252 newLIR4(cUnit, kMipsExt, reg0, reg0, 0, 31-1 /* size-1 */);
254 newLIR2(cUnit, kMipsSll, reg0, 1);
255 newLIR2(cUnit, kMipsSrl, reg0, 1);
257 storeWordDisp(cUnit, rSELF, offset, reg0);
259 dvmCompilerClobber(cUnit, reg0);
289 int reg0 = loadValue(cUnit, rlSrc1, kCoreReg).lowReg; local
293 newLIR3(cUnit, kMipsSlt, tReg, reg0, reg1);
296 newLIR3(cUnit, kMipsSlt, tReg, reg1, reg0);
    [all...]
  /external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/r200/
r200_fragshader.c 48 GLuint reg0 = 0; local
76 reg0 |= (((index - GL_REG_0_ATI)*2) + 10 + useOddSrc) << (5*argPos);
79 reg0 |= (R200_TXC_ARG_A_TFACTOR_COLOR + useOddSrc) << (5*argPos);
84 reg0 |= (R200_TXC_ARG_A_TFACTOR1_COLOR + useOddSrc) << (5*argPos);
89 reg0 |= (R200_TXC_ARG_A_DIFFUSE_COLOR + useOddSrc) << (5*argPos);
92 reg0 |= (R200_TXC_ARG_A_SPECULAR_COLOR + useOddSrc) << (5*argPos);
96 reg0 |= R200_TXC_COMP_ARG_A << (4*argPos);
100 reg0 ^= R200_TXC_COMP_ARG_A << (4*argPos);
102 reg0 |= R200_TXC_BIAS_ARG_A << (4*argPos);
104 reg0 |= R200_TXC_SCALE_ARG_A << (4*argPos)
    [all...]
  /external/mesa3d/src/mesa/drivers/dri/r200/
r200_fragshader.c 48 GLuint reg0 = 0; local
76 reg0 |= (((index - GL_REG_0_ATI)*2) + 10 + useOddSrc) << (5*argPos);
79 reg0 |= (R200_TXC_ARG_A_TFACTOR_COLOR + useOddSrc) << (5*argPos);
84 reg0 |= (R200_TXC_ARG_A_TFACTOR1_COLOR + useOddSrc) << (5*argPos);
89 reg0 |= (R200_TXC_ARG_A_DIFFUSE_COLOR + useOddSrc) << (5*argPos);
92 reg0 |= (R200_TXC_ARG_A_SPECULAR_COLOR + useOddSrc) << (5*argPos);
96 reg0 |= R200_TXC_COMP_ARG_A << (4*argPos);
100 reg0 ^= R200_TXC_COMP_ARG_A << (4*argPos);
102 reg0 |= R200_TXC_BIAS_ARG_A << (4*argPos);
104 reg0 |= R200_TXC_SCALE_ARG_A << (4*argPos)
    [all...]
  /external/pixman/pixman/
pixman-arm-simd-asm.h 99 .macro pixldst op, cond=al, numbytes, reg0, reg1, reg2, reg3, base, unaligned=0 variable
102 op&r&cond WK&reg0, [base], #4
107 op&m&cond&ia base!, {WK&reg0,WK&reg1,WK&reg2,WK&reg3} variable
111 op&r&cond WK&reg0, [base], #4
114 op&m&cond&ia base!, {WK&reg0,WK&reg1} variable
117 op&r&cond WK&reg0, [base], #4
119 op&r&cond&h WK&reg0, [base], #2
121 op&r&cond&b WK&reg0, [base], #1
127 .macro pixst_baseupdated cond, numbytes, reg0, reg1, reg2, reg3, base variable
129 stm&cond&db base, {WK&reg0,WK&reg1,WK&reg2,WK&reg3 variable
131 stm&cond&db base, {WK&reg0,WK&reg1} variable
    [all...]
  /hardware/invensense/60xx/mlsdk/mllite/
ml.c 1088 unsigned char reg0[4] = { 0, 0, 0, 0 }; local
    [all...]
  /prebuilts/tools/common/m2/internal/com/google/code/findbugs/findbugs/2.0.1/
findbugs-2.0.1.jar 

Completed in 479 milliseconds