OpenGrok
Home
Sort by relevance
Sort by last modified time
Full Search
Definition
Symbol
File Path
History
|
|
Help
Searched
refs:Accesses
(Results
1 - 7
of
7
) sorted by null
/external/llvm/lib/Transforms/Vectorize/
LoopVectorize.cpp
362
/// will change the order of memory
accesses
in a way that will change the
[
all
...]
/external/oprofile/events/mips/24K/
events
24
event:0x5 counters:0 um:zero minimum:500 name:ITLB_ACCESSES : 5-0 Instruction micro-TLB
accesses
25
event:0x6 counters:0 um:zero minimum:500 name:DTLB_ACCESSES : 6-0 Data micro-TLB
accesses
26
event:0x7 counters:0 um:zero minimum:500 name:JTLB_INSN_ACCESSES : 7-0 Joint TLB instruction
accesses
27
event:0x8 counters:0 um:zero minimum:500 name:JTLB_DATA_ACCESSES : 8-0 Joint TLB data (non-instruction)
accesses
28
event:0x9 counters:0 um:zero minimum:500 name:ICACHE_ACCESSES : 9-0 Instruction cache
accesses
29
event:0xa counters:0 um:zero minimum:500 name:DCACHE_ACCESSES : 10-0 Data cache
accesses
40
event:0x16 counters:0 um:zero minimum:500 name:L2_CACHE_MISSES : 22-0 L2 cache
accesses
that missed in the cache
103
event:0x415 counters:1 um:zero minimum:500 name:L2_CACHE_ACCESSES : 21-1
Accesses
to the L2 cache
/external/oprofile/events/mips/34K/
events
24
event:0x5 counters:0 um:zero minimum:500 name:ITLB_ACCESSES : 5-0 Instruction micro-TLB
accesses
25
event:0x6 counters:0 um:zero minimum:500 name:DTLB_ACCESSES : 6-0 Data micro-TLB
accesses
26
event:0x7 counters:0 um:zero minimum:500 name:JTLB_INSN_ACCESSES : 7-0 Joint TLB instruction
accesses
27
event:0x8 counters:0 um:zero minimum:500 name:JTLB_DATA_ACCESSES : 8-0 Joint TLB data (non-instruction)
accesses
28
event:0x9 counters:0 um:zero minimum:500 name:ICACHE_ACCESSES : 9-0 Instruction cache
accesses
29
event:0xa counters:0 um:zero minimum:500 name:DCACHE_ACCESSES : 10-0 Data cache
accesses
40
event:0x16 counters:0 um:zero minimum:500 name:L2_CACHE_MISSES : 22-0 L2 cache
accesses
that missed in the cache
111
event:0x415 counters:1 um:zero minimum:500 name:L2_CACHE_ACCESSES : 21-1
Accesses
to the L2 cache
/external/oprofile/events/x86-64/family11h/
events
38
event:0x40 counters:0,1,2,3 um:zero minimum:500 name:DATA_CACHE_ACCESSES : Data cache
accesses
46
event:0x47 counters:0,1,2,3 um:zero minimum:500 name:MISALIGNED_ACCESSES : Misaligned
Accesses
115
event:0xe0 counters:0,1,2,3 um:dramaccess minimum:500 name:DRAM_ACCESSES : DRAM
accesses
/external/oprofile/events/x86-64/hammer/
events
38
event:0x40 counters:0,1,2,3 um:zero minimum:500 name:DATA_CACHE_ACCESSES : Data cache
accesses
46
event:0x47 counters:0,1,2,3 um:zero minimum:500 name:MISALIGNED_ACCESSES : Misaligned
Accesses
110
event:0xe0 counters:0,1,2,3 um:page_access minimum:500 name:DRAM_ACCESSES : DRAM
accesses
/external/oprofile/events/mips/1004K/
events
24
event:0x5 counters:0 um:zero minimum:500 name:ITLB_ACCESSES : 5-0 Instruction micro-TLB
accesses
25
event:0x6 counters:0 um:zero minimum:500 name:DTLB_ACCESSES : 6-0 Data micro-TLB
accesses
26
event:0x7 counters:0 um:zero minimum:500 name:JTLB_INSN_ACCESSES : 7-0 Joint TLB instruction
accesses
27
event:0x8 counters:0 um:zero minimum:500 name:JTLB_DATA_ACCESSES : 8-0 Joint TLB data (non-instruction)
accesses
28
event:0x9 counters:0 um:zero minimum:500 name:ICACHE_ACCESSES : 9-0 Instruction cache
accesses
29
event:0xa counters:0 um:zero minimum:500 name:DCACHE_ACCESSES : 10-0 Data cache
accesses
40
event:0x16 counters:0 um:zero minimum:500 name:L2_CACHE_MISSES : 22-0 L2 cache
accesses
that missed in the cache
119
event:0x415 counters:1 um:zero minimum:500 name:L2_CACHE_ACCESSES : 21-1
Accesses
to the L2 cache
/external/oprofile/events/mips/74K/
events
22
event:0x4 counters:0,2 um:zero minimum:500 name:ITLB_ACCESSES : 4-0 Instruction micro-TLB
accesses
24
event:0x6 counters:0,2 um:zero minimum:500 name:ICACHE_ACCESSES : 6-0 Instruction cache
accesses
including speculative instructions
41
event:0x17 counters:0,2 um:zero minimum:500 name:DCACHE_LOAD_ACCESSES : 23-0 Counts all
accesses
to the data cache caused by load instructions
43
event:0x19 counters:0,2 um:zero minimum:500 name:JTLB_DATA_ACCESSES : 25-0 Joint TLB data (non-instruction)
accesses
117
event:0x417 counters:1,3 um:zero minimum:500 name:DCACHE_ACCESSES : 23-1 Data cache
accesses
122
event:0x41c counters:1,3 um:zero minimum:500 name:L2_CACHE_ACCESSES : 28-1
Accesses
to the L2 cache
Completed in 62 milliseconds