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    Searched refs:CP0SRSC1_SRS5 (Results 1 - 2 of 2) sorted by null

/external/qemu/target-mips/
cpu.h	243 #define CP0SRSC1_SRS5 10
translate_init.c	294 (0x3fe << CP0SRSC1_SRS5) | (0x3fe << CP0SRSC1_SRS4),

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