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    Searched refs:Chan (Results 1 - 7 of 7) sorted by null

  /external/llvm/lib/Target/R600/
R600ExpandSpecialInstrs.cpp 98 for (unsigned Chan = 0; Chan < 4; ++Chan) {
101 if (Chan < 2)
102 DstReg = MI.getOperand(Chan).getReg();
104 DstReg = Chan == 2 ? AMDGPU::T0_Z : AMDGPU::T0_W;
107 DstReg, MI.getOperand(3 + (Chan % 2)).getReg(), PReg);
109 if (Chan > 0) {
112 if (Chan >= 2)
114 if (Chan != 3
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R600OptimizeVectorRegisters.cpp 66 unsigned Chan = Instr->getOperand(i + 1).getImm();
68 UndefReg.push_back(Chan);
70 RegToChan[MO.getReg()] = Chan;
165 unsigned Chan) {
167 if (RemapChan[j].first == Chan)
170 llvm_unreachable("Chan wasn't reassigned");
189 unsigned Chan = getReassignedChan(RemapChan, Swizzle);
195 .addImm(Chan);
196 UpdatedRegToChan[SubReg] = Chan;
198 std::find(UpdatedUndef.begin(), UpdatedUndef.end(), Chan);
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R600MachineScheduler.cpp 457 for (int Chan = 3; Chan > -1; --Chan) {
458 bool isOccupied = OccupedSlotsMask & (1 << Chan);
460 SUnit *SU = AttemptFillSlot(Chan);
462 OccupedSlotsMask |= (1 << Chan);
R600EmitClauseMarkers.cpp 118 unsigned Chan = Sel & 3, Index = ((Sel >> 2) - 512) & 31;
119 unsigned KCacheIndex = Index * 4 + Chan;
R600InstrInfo.cpp 313 unsigned Chan = RI.getHWRegChan(Reg);
314 Result.push_back(std::pair<int, unsigned>(Index, Chan));
576 unsigned Chan = RI.getHWRegChan(Src.first->getReg());
577 Consts.push_back((Index << 2) | Chan);
1019 for (unsigned Chan = 0; Chan < StackWidth; ++Chan) {
1020 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister((4 * Index) + Chan);
    [all...]
  /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
R600ExpandSpecialInstrs.cpp 95 for (unsigned Chan = 0; Chan < 4; Chan++) {
105 unsigned SubRegIndex = TRI.getSubRegFromChannel(Chan);
110 unsigned SubRegIndex0 = TRI.getSubRegFromChannel(CubeSrcSwz[Chan]);
111 unsigned SubRegIndex1 = TRI.getSubRegFromChannel(CubeSrcSwz[3 - Chan]);
119 unsigned SubRegIndex = TRI.getSubRegFromChannel(Chan);
124 Flags |= (Chan != TRI.getHWRegChan(DstReg) ? MO_FLAG_MASK : 0);
126 DstReg = AMDGPU::R600_TReg32RegClass.getRegister((DstBase * 4) + Chan);
130 Flags |= (Chan != 3 ? MO_FLAG_NOT_LAST : 0)
    [all...]
  /external/mesa3d/src/gallium/drivers/radeon/
R600ExpandSpecialInstrs.cpp 95 for (unsigned Chan = 0; Chan < 4; Chan++) {
105 unsigned SubRegIndex = TRI.getSubRegFromChannel(Chan);
110 unsigned SubRegIndex0 = TRI.getSubRegFromChannel(CubeSrcSwz[Chan]);
111 unsigned SubRegIndex1 = TRI.getSubRegFromChannel(CubeSrcSwz[3 - Chan]);
119 unsigned SubRegIndex = TRI.getSubRegFromChannel(Chan);
124 Flags |= (Chan != TRI.getHWRegChan(DstReg) ? MO_FLAG_MASK : 0);
126 DstReg = AMDGPU::R600_TReg32RegClass.getRegister((DstBase * 4) + Chan);
130 Flags |= (Chan != 3 ? MO_FLAG_NOT_LAST : 0)
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