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Searched
refs:ImplicitDefs
(Results
1 - 12
of
12
) sorted by null
/external/llvm/include/llvm/MC/
MCInstrDesc.h
146
const uint16_t *
ImplicitDefs
; // Registers implicitly defined by this instr
505
return
ImplicitDefs
;
510
if (
ImplicitDefs
== 0) return 0;
512
for (;
ImplicitDefs
[i]; ++i) /*empty*/;
529
if (const uint16_t *ImpDefs =
ImplicitDefs
)
/external/llvm/lib/CodeGen/SelectionDAG/
FastISel.cpp
[
all
...]
ScheduleDAGFast.cpp
436
assert(MCID.
ImplicitDefs
&& "Physical reg def must be in implicit def list!");
514
if (!MCID.
ImplicitDefs
)
ScheduleDAGSDNodes.cpp
125
II.
ImplicitDefs
[ResNo - II.getNumDefs()] == Reg) {
[
all
...]
ScheduleDAGRRList.cpp
[
all
...]
/external/llvm/utils/TableGen/
CodeGenInstruction.cpp
328
ImplicitDefs
= R->getValueAsListOfDefs("Defs");
346
if (
ImplicitDefs
.empty()) return MVT::Other;
349
Record *FirstImplicitDef =
ImplicitDefs
[0];
CodeGenInstruction.h
213
///
ImplicitDefs
/ImplicitUses - These are lists of registers that are
215
std::vector<Record*>
ImplicitDefs
, ImplicitUses;
DAGISelMatcherGen.cpp
[
all
...]
CodeGenDAGPatterns.cpp
[
all
...]
/external/llvm/lib/Target/ARM/
ARMFastISel.cpp
317
.addReg(II.
ImplicitDefs
[0]));
339
.addReg(II.
ImplicitDefs
[0]));
364
.addReg(II.
ImplicitDefs
[0]));
386
.addReg(II.
ImplicitDefs
[0]));
408
.addReg(II.
ImplicitDefs
[0]));
433
.addReg(II.
ImplicitDefs
[0]));
452
.addReg(II.
ImplicitDefs
[0]));
472
.addReg(II.
ImplicitDefs
[0]));
[
all
...]
/external/llvm/lib/CodeGen/
MachineInstr.cpp
521
if (MCID->
ImplicitDefs
)
[
all
...]
/external/llvm/lib/Target/PowerPC/
PPCInstrInfo.cpp
[
all
...]
Completed in 378 milliseconds