/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/i965/ |
brw_program.c | 177 struct prog_instruction *inst = prog->Instructions + i; 180 if (prog->Instructions[i].Opcode == OPCODE_CAL) { 188 if (prog->Instructions[i].Opcode == OPCODE_RET) { 196 if (prog->Instructions[i].SrcReg[r].RelAddr && 197 prog->Instructions[i].SrcReg[r].File == PROGRAM_INPUT) { 205 prog->Instructions[i].DstReg.RelAddr && 206 prog->Instructions[i].DstReg.File == PROGRAM_OUTPUT) { 212 if ((prog->Instructions[i].DstReg.RelAddr && 213 prog->Instructions[i].DstReg.File == PROGRAM_TEMPORARY) || 214 (prog->Instructions[i].SrcReg[0].RelAddr & [all...] |
/external/mesa3d/src/mesa/drivers/dri/i965/ |
brw_program.c | 177 struct prog_instruction *inst = prog->Instructions + i; 180 if (prog->Instructions[i].Opcode == OPCODE_CAL) { 188 if (prog->Instructions[i].Opcode == OPCODE_RET) { 196 if (prog->Instructions[i].SrcReg[r].RelAddr && 197 prog->Instructions[i].SrcReg[r].File == PROGRAM_INPUT) { 205 prog->Instructions[i].DstReg.RelAddr && 206 prog->Instructions[i].DstReg.File == PROGRAM_OUTPUT) { 212 if ((prog->Instructions[i].DstReg.RelAddr && 213 prog->Instructions[i].DstReg.File == PROGRAM_TEMPORARY) || 214 (prog->Instructions[i].SrcReg[0].RelAddr & [all...] |
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/compiler/ |
radeon_program.c | 46 * instructions emitted by transformations are not transformed. 57 struct rc_instruction * inst = c->Program.Instructions.Next; 59 while(inst != &c->Program.Instructions) { 114 for(inst = c->Program.Instructions.Next; 115 inst != &c->Program.Instructions; inst = inst->Next) { 209 * Return the number of instructions in the program. 216 for(inst = c->Program.Instructions.Next; 217 inst != &c->Program.Instructions; 222 c->Program.Instructions.IP = 0xcafedead;
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radeon_remove_constants.c | 85 for (struct rc_instruction *inst = c->Program.Instructions.Next; 86 inst != &c->Program.Instructions; inst = inst->Next) { 127 for (struct rc_instruction *inst = c->Program.Instructions.Next; 128 inst != &c->Program.Instructions; inst = inst->Next) {
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radeon_compiler.c | 40 c->Program.Instructions.Prev = &c->Program.Instructions; 41 c->Program.Instructions.Next = &c->Program.Instructions; 42 c->Program.Instructions.U.I.Opcode = RC_OPCODE_ILLEGAL_OPCODE; 108 * in program instructions. 117 for(inst = c->Program.Instructions.Next; inst != &c->Program.Instructions; inst = inst->Next) 144 for(inst = c->Program.Instructions.Next; inst != &c->Program.Instructions; inst = inst->Next) [all...] |
radeon_rename_regs.c | 44 * This function assumes all the instructions are still of type 56 for(inst = c->Program.Instructions.Next; 57 inst != &c->Program.Instructions;
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radeon_dataflow_deadcode.c | 61 struct instruction_state * Instructions; 155 struct instruction_state * insts = &s->Instructions[inst->IP]; 225 s.Instructions = memory_pool_malloc(&c->Pool, sizeof(struct instruction_state)*nr_instructions); 226 memset(s.Instructions, 0, sizeof(struct instruction_state)*nr_instructions); 230 for(struct rc_instruction * inst = c->Program.Instructions.Prev; 231 inst != &c->Program.Instructions; 313 for(struct rc_instruction * inst = c->Program.Instructions.Next; 314 inst != &c->Program.Instructions; 324 inst->U.I.DstReg.WriteMask = s.Instructions[ip].WriteMask; 325 if (s.Instructions[ip].WriteMask [all...] |
radeon_pair_dead_sources.c | 44 for (inst = c->Program.Instructions.Next; 45 inst != &c->Program.Instructions;
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/external/mesa3d/src/gallium/drivers/r300/compiler/ |
radeon_program.c | 46 * instructions emitted by transformations are not transformed. 57 struct rc_instruction * inst = c->Program.Instructions.Next; 59 while(inst != &c->Program.Instructions) { 114 for(inst = c->Program.Instructions.Next; 115 inst != &c->Program.Instructions; inst = inst->Next) { 209 * Return the number of instructions in the program. 216 for(inst = c->Program.Instructions.Next; 217 inst != &c->Program.Instructions; 222 c->Program.Instructions.IP = 0xcafedead;
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radeon_remove_constants.c | 85 for (struct rc_instruction *inst = c->Program.Instructions.Next; 86 inst != &c->Program.Instructions; inst = inst->Next) { 127 for (struct rc_instruction *inst = c->Program.Instructions.Next; 128 inst != &c->Program.Instructions; inst = inst->Next) {
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radeon_compiler.c | 40 c->Program.Instructions.Prev = &c->Program.Instructions; 41 c->Program.Instructions.Next = &c->Program.Instructions; 42 c->Program.Instructions.U.I.Opcode = RC_OPCODE_ILLEGAL_OPCODE; 108 * in program instructions. 117 for(inst = c->Program.Instructions.Next; inst != &c->Program.Instructions; inst = inst->Next) 144 for(inst = c->Program.Instructions.Next; inst != &c->Program.Instructions; inst = inst->Next) [all...] |
radeon_rename_regs.c | 44 * This function assumes all the instructions are still of type 56 for(inst = c->Program.Instructions.Next; 57 inst != &c->Program.Instructions;
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radeon_dataflow_deadcode.c | 61 struct instruction_state * Instructions; 155 struct instruction_state * insts = &s->Instructions[inst->IP]; 225 s.Instructions = memory_pool_malloc(&c->Pool, sizeof(struct instruction_state)*nr_instructions); 226 memset(s.Instructions, 0, sizeof(struct instruction_state)*nr_instructions); 230 for(struct rc_instruction * inst = c->Program.Instructions.Prev; 231 inst != &c->Program.Instructions; 313 for(struct rc_instruction * inst = c->Program.Instructions.Next; 314 inst != &c->Program.Instructions; 324 inst->U.I.DstReg.WriteMask = s.Instructions[ip].WriteMask; 325 if (s.Instructions[ip].WriteMask [all...] |
radeon_pair_dead_sources.c | 44 for (inst = c->Program.Instructions.Next; 45 inst != &c->Program.Instructions;
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/external/llvm/utils/TableGen/ |
CodeGenTarget.h | 68 mutable DenseMap<const Record*, CodeGenInstruction*> Instructions; 150 if (Instructions.empty()) ReadInstructions(); 151 return Instructions; 156 if (Instructions.empty()) ReadInstructions(); 158 Instructions.find(InstRec); 159 assert(I != Instructions.end() && "Not an instruction"); 163 /// getInstructionsByEnumValue - Return all of the instructions defined by the
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/external/llvm/lib/MC/ |
MCStreamer.cpp | 265 CurFrame->Instructions.push_back(Instruction); 273 CurFrame->Instructions.push_back(Instruction); 281 CurFrame->Instructions.push_back(Instruction); 289 CurFrame->Instructions.push_back(Instruction); 297 CurFrame->Instructions.push_back(Instruction); 305 CurFrame->Instructions.push_back(Instruction); 327 CurFrame->Instructions.push_back(Instruction); 335 CurFrame->Instructions.push_back(Instruction); 343 CurFrame->Instructions.push_back(Instruction); 351 CurFrame->Instructions.push_back(Instruction) [all...] |
/external/chromium_org/third_party/mesa/src/src/mesa/program/ |
arbprogparse.c | 36 The instructions we emit will use six kinds of source registers: 125 if (program->Base.Instructions) 126 free(program->Base.Instructions); 127 program->Base.Instructions = prog.Instructions; 133 /* Append fog instructions now if the program has "OPTION ARB_fog_exp" 205 if (program->Base.Instructions) 206 free(program->Base.Instructions); 207 program->Base.Instructions = prog.Instructions; [all...] |
programopt.c | 44 * This function inserts instructions for coordinate modelview * projection 73 /* Alloc storage for new instructions */ 82 * Generated instructions: 102 /* Append original instructions after new instructions */ 103 _mesa_copy_instructions (newInst + 4, vprog->Base.Instructions, origLen); 105 /* free old instructions */ 106 _mesa_free_instructions(vprog->Base.Instructions, origLen); 108 /* install new instructions */ 109 vprog->Base.Instructions = newInst [all...] |
/external/mesa3d/src/mesa/program/ |
arbprogparse.c | 36 The instructions we emit will use six kinds of source registers: 125 if (program->Base.Instructions) 126 free(program->Base.Instructions); 127 program->Base.Instructions = prog.Instructions; 133 /* Append fog instructions now if the program has "OPTION ARB_fog_exp" 205 if (program->Base.Instructions) 206 free(program->Base.Instructions); 207 program->Base.Instructions = prog.Instructions; [all...] |
programopt.c | 44 * This function inserts instructions for coordinate modelview * projection 73 /* Alloc storage for new instructions */ 82 * Generated instructions: 102 /* Append original instructions after new instructions */ 103 _mesa_copy_instructions (newInst + 4, vprog->Base.Instructions, origLen); 105 /* free old instructions */ 106 _mesa_free_instructions(vprog->Base.Instructions, origLen); 108 /* install new instructions */ 109 vprog->Base.Instructions = newInst [all...] |
/external/llvm/lib/DebugInfo/ |
DWARFDebugFrame.cpp | 38 /// \brief Parse and store a sequence of CFI instructions from our data 47 /// \brief Dump the entry's instructions to the given output stream. 63 /// An entry may contain CFI instructions. An instruction consists of an 75 std::vector<Instruction> Instructions; 78 /// operands to the Instructions vector. 80 Instructions.push_back(Instruction(Opcode)); 84 Instructions.push_back(Instruction(Opcode)); 85 Instructions.back().Ops.push_back(Operand1); 89 Instructions.push_back(Instruction(Opcode)); 90 Instructions.back().Ops.push_back(Operand1) [all...] |
/external/mdnsresponder/mDNSShared/ |
dnsextd.conf | 3 // Instructions for /etc/dnsextd.conf (this file) 14 // Instructions for /etc/named.conf
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/external/chromium_org/sandbox/linux/seccomp-bpf/ |
codegen.h | 19 typedef std::vector<Instruction *> Instructions; 26 // graph of BPF instructions into a well-formed stream of BPF instructions. 28 // the limit of 255 instructions imposed by the instruction set. 31 // build a DAG of Instructions. They'll eventually call Compile() to convert 34 // Instructions can be chained at the time when they are created, or they 65 // Create a new instruction. Instructions form a DAG. The instruction objects 75 // Join two (sequences of) instructions. This is useful, if the "next" 80 // Traverse the graph of instructions and visit each instruction once. 89 // Compiles the graph of instructions into a BPF program that can be passe [all...] |
/external/llvm/include/llvm/MC/ |
MCWin64EH.h | 68 Instructions() {} 79 std::vector<MCWin64EHInstruction> Instructions;
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/external/oprofile/events/mips/5K/ |
events | 16 event:0x1 counters:0 um:zero minimum:500 name:INSN_FETCHED : Instructions fetched 23 event:0xe counters:0 um:zero minimum:500 name:DUAL_ISSUED_INSNS : Dual issued instructions executed 24 event:0xf counters:0 um:zero minimum:500 name:INSNS_EXECED : Instructions executed 29 event:0x1 counters:1 um:zero minimum:500 name:INSNS_EXECED : Instructions executed 30 event:0x5 counters:1 um:zero minimum:500 name:FP_INSNS_EXECED : Floating-point instructions executed 36 event:0xf counters:1 um:zero minimum:500 name:COP2_INSNS_EXECED : COP2 instructions executed
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