| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/nv50/codegen/ |
| nv50_ir_lowering_nv50.cpp | 72 i[2] = bld->mkOp2(OP_MUL, fTy, t[0], a[0], b[1]);
169 if (i->op == OP_ADD || i->op == OP_MUL || i->op == OP_FMA ||
367 mul = bld.mkOp2(OP_MUL, add->sType, res, add->getSrc(0), add->getSrc(1));
417 bld.mkOp2(OP_MUL, TYPE_F32, (qf = bld.getSSA()), af, bf)->rnd = ROUND_Z;
422 bld.mkOp2(OP_MUL, TYPE_U32, (t = bld.getSSA()), q0, b));
427 bld.mkOp2(OP_MUL, TYPE_F32, (qRf = bld.getSSA()), aR, bf)->rnd = ROUND_Z;
434 bld.mkOp2(OP_MUL, TYPE_U32, (t = bld.getSSA()), q, b));
472 expandIntegerMUL(&bld, bld.mkOp2(OP_MUL, TYPE_U32, m, q, mod->getSrc(1)));
498 case OP_MUL:
955 i->op = OP_MUL;
[all...] |
| nv50_ir_peephole.cpp | 400 case OP_MUL:
561 assert(mul2->op == OP_MUL && mul2->dType == TYPE_F32);
565 if (!mul2->src(t).mod && insn->op == OP_MUL && insn->dType == TYPE_F32)
579 if (prog->getTarget()->isPostMultiplySupported(OP_MUL, f, e)) {
602 if (insn->op == OP_MUL && insn->dType == TYPE_F32)
605 if (mul2 && prog->getTarget()->isPostMultiplySupported(OP_MUL, f, e)) {
621 case OP_MUL:
703 mul = bld.mkOp2(OP_MUL, TYPE_U32, tA, i->getSrc(0),
860 i->op != OP_MUL) ||
1003 const operation srcOp = toOp == OP_SAD ? OP_SAD : OP_MUL;
[all...] |
| nv50_ir_from_sm4.cpp | 393 case SM4_OPCODE_IMUL: return OP_MUL;
409 case SM4_OPCODE_MUL: return OP_MUL;
434 case SM4_OPCODE_UMUL: return OP_MUL;
479 case SM4_OPCODE_DMUL: return OP_MUL;
[all...] |
| nv50_ir_target_nv50.cpp | 87 { OP_MUL, 0x3, 0x0, 0x0, 0x0, 0x2, 0x1, 0x1, 0x2 },
315 if ((i->op == OP_MUL || i->op == OP_MAD) && !isFloatType(i->dType)) {
|
| nv50_ir_from_tgsi.cpp | [all...] |
| nv50_ir_emit_nv50.cpp | [all...] |
| nv50_ir.h | 53 OP_MUL,
|
| /external/mesa3d/src/gallium/drivers/nv50/codegen/ |
| nv50_ir_lowering_nv50.cpp | 72 i[2] = bld->mkOp2(OP_MUL, fTy, t[0], a[0], b[1]);
169 if (i->op == OP_ADD || i->op == OP_MUL || i->op == OP_FMA ||
367 mul = bld.mkOp2(OP_MUL, add->sType, res, add->getSrc(0), add->getSrc(1));
417 bld.mkOp2(OP_MUL, TYPE_F32, (qf = bld.getSSA()), af, bf)->rnd = ROUND_Z;
422 bld.mkOp2(OP_MUL, TYPE_U32, (t = bld.getSSA()), q0, b));
427 bld.mkOp2(OP_MUL, TYPE_F32, (qRf = bld.getSSA()), aR, bf)->rnd = ROUND_Z;
434 bld.mkOp2(OP_MUL, TYPE_U32, (t = bld.getSSA()), q, b));
472 expandIntegerMUL(&bld, bld.mkOp2(OP_MUL, TYPE_U32, m, q, mod->getSrc(1)));
498 case OP_MUL:
955 i->op = OP_MUL;
[all...] |
| nv50_ir_peephole.cpp | 400 case OP_MUL:
561 assert(mul2->op == OP_MUL && mul2->dType == TYPE_F32);
565 if (!mul2->src(t).mod && insn->op == OP_MUL && insn->dType == TYPE_F32)
579 if (prog->getTarget()->isPostMultiplySupported(OP_MUL, f, e)) {
602 if (insn->op == OP_MUL && insn->dType == TYPE_F32)
605 if (mul2 && prog->getTarget()->isPostMultiplySupported(OP_MUL, f, e)) {
621 case OP_MUL:
703 mul = bld.mkOp2(OP_MUL, TYPE_U32, tA, i->getSrc(0),
860 i->op != OP_MUL) ||
1003 const operation srcOp = toOp == OP_SAD ? OP_SAD : OP_MUL;
[all...] |
| nv50_ir_from_sm4.cpp | 393 case SM4_OPCODE_IMUL: return OP_MUL;
409 case SM4_OPCODE_MUL: return OP_MUL;
434 case SM4_OPCODE_UMUL: return OP_MUL;
479 case SM4_OPCODE_DMUL: return OP_MUL;
[all...] |
| nv50_ir_target_nv50.cpp | 87 { OP_MUL, 0x3, 0x0, 0x0, 0x0, 0x2, 0x1, 0x1, 0x2 },
315 if ((i->op == OP_MUL || i->op == OP_MAD) && !isFloatType(i->dType)) {
|
| nv50_ir_from_tgsi.cpp | [all...] |
| nv50_ir_emit_nv50.cpp | [all...] |
| /system/core/libpixelflinger/codeflinger/ |
| mips_opcode.h | 260 #define OP_MUL 002 /* QED */
|
| mips_disassem.c | 307 if (i.RType.func == OP_MUL)
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/nvc0/codegen/ |
| nv50_ir_target_nvc0.cpp | 219 { OP_MUL, 0x3, 0x0, 0x0, 0x8, 0x2, 0x2 | 0x8 },
528 if (op != OP_MUL)
558 if (i->op == OP_MUL && i->dType != TYPE_F32)
588 case OP_MUL:
620 case OP_MUL:
|
| nv50_ir_lowering_nvc0.cpp | 491 if (i->op == OP_ADD || i->op == OP_MUL || i->op == OP_FMA ||
940 i->op = OP_MUL;
952 bld.mkOp2(OP_MUL, TYPE_F32, value, i->getSrc(0), value);
954 bld.mkOp2(OP_MUL, TYPE_F32, value, i->getSrc(1), value);
965 i->op = OP_MUL;
977 bld.mkOp2(OP_MUL, TYPE_F32, val, i->getSrc(1), val)->dnz = 1;
[all...] |
| nv50_ir_emit_nvc0.cpp | [all...] |
| /external/mesa3d/src/gallium/drivers/nvc0/codegen/ |
| nv50_ir_target_nvc0.cpp | 219 { OP_MUL, 0x3, 0x0, 0x0, 0x8, 0x2, 0x2 | 0x8 },
528 if (op != OP_MUL)
558 if (i->op == OP_MUL && i->dType != TYPE_F32)
588 case OP_MUL:
620 case OP_MUL:
|
| nv50_ir_lowering_nvc0.cpp | 491 if (i->op == OP_ADD || i->op == OP_MUL || i->op == OP_FMA ||
940 i->op = OP_MUL;
952 bld.mkOp2(OP_MUL, TYPE_F32, value, i->getSrc(0), value);
954 bld.mkOp2(OP_MUL, TYPE_F32, value, i->getSrc(1), value);
965 i->op = OP_MUL;
977 bld.mkOp2(OP_MUL, TYPE_F32, val, i->getSrc(1), val)->dnz = 1;
[all...] |
| nv50_ir_emit_nvc0.cpp | [all...] |
| /sdk/emulator/qtools/ |
| opcode.h | 42 OP_MUL,
|
| armdis.cpp | 114 case OP_MUL:
804 return OP_MUL;
|
| /external/chromium_org/base/test/ |
| trace_event_analyzer.h | 440 OP_MUL,
|
| trace_event_analyzer.cc | 375 case OP_MUL:
593 return Query(*this, rhs, OP_MUL);
|
