| /external/llvm/lib/MC/ |
| MCInstrAnalysis.cpp | 16 Info->get(Inst.getOpcode()).OpInfo[0].OperandType != MCOI::OPERAND_PCREL)
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/nv50/codegen/ |
| nv50_ir_target.h | 139 struct OpInfo
141 OpInfo *variants;
161 inline const OpInfo& getOpInfo(const Instruction *) const;
162 inline const OpInfo& getOpInfo(const operation) const;
210 OpInfo opInfo[OP_LAST + 1];
213 const Target::OpInfo& Target::getOpInfo(const Instruction *insn) const
215 return opInfo[MIN2(insn->op, OP_LAST)];
218 const Target::OpInfo& Target::getOpInfo(const operation op) const
220 return opInfo[op]
[all...] |
| /external/mesa3d/src/gallium/drivers/nv50/codegen/ |
| nv50_ir_target.h | 139 struct OpInfo
141 OpInfo *variants;
161 inline const OpInfo& getOpInfo(const Instruction *) const;
162 inline const OpInfo& getOpInfo(const operation) const;
210 OpInfo opInfo[OP_LAST + 1];
213 const Target::OpInfo& Target::getOpInfo(const Instruction *insn) const
215 return opInfo[MIN2(insn->op, OP_LAST)];
218 const Target::OpInfo& Target::getOpInfo(const operation op) const
220 return opInfo[op]
[all...] |
| /external/llvm/include/llvm/Bitcode/ |
| BitCodes.h | 181 void Add(const BitCodeAbbrevOp &OpInfo) {
182 OperandList.push_back(OpInfo);
|
| /external/llvm/utils/TableGen/ |
| AsmWriterInst.cpp | 203 CGIOperandList::OperandInfo OpInfo = CGI.Operands[OpNo];
205 unsigned MIOp = OpInfo.MIOperandNo;
206 Operands.push_back(AsmWriterOperand(OpInfo.PrinterMethodName,
|
| AsmMatcherEmitter.cpp | [all...] |
| FixedLenDecoderEmitter.cpp | 458 const OperandInfo &OpInfo) const;
[all...] |
| InstrInfoEmitter.cpp | 58 const OperandInfoMapTy &OpInfo,
438 const OperandInfoMapTy &OpInfo,
515 OS << "OperandInfo" << OpInfo.find(OperandInfo)->second;
|
| /external/llvm/include/llvm/MC/ |
| MCInstrDesc.h | 147 const MCOperandInfo *OpInfo; // 'NumOperands' entries about operands
154 (OpInfo[OpNum].Constraints & (1 << Constraint))) {
156 return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
567 if (OpInfo[i].isPredicate())
|
| /external/llvm/lib/Analysis/ |
| CostModel.cpp | 92 TargetTransformInfo::OperandValueKind OpInfo =
99 OpInfo = TargetTransformInfo::OK_UniformConstantValue;
103 OpInfo = TargetTransformInfo::OK_UniformConstantValue;
105 return OpInfo;
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| TargetLowering.cpp | [all...] |
| SelectionDAGBuilder.cpp | [all...] |
| /external/clang/lib/CodeGen/ |
| CGExprComplex.cpp | 639 BinOpInfo OpInfo;
644 OpInfo.Ty = E->getComputationResultType();
647 assert(OpInfo.Ty->isAnyComplexType());
648 assert(CGF.getContext().hasSameUnqualifiedType(OpInfo.Ty,
650 OpInfo.RHS = Visit(E->getRHS());
657 OpInfo.LHS = EmitComplexToComplexCast(LHSVal, LHSTy, OpInfo.Ty);
660 OpInfo.LHS = EmitScalarToComplexCast(LHSVal, LHSTy, OpInfo.Ty);
664 ComplexPairTy Result = (this->*Func)(OpInfo);
[all...] |
| CGExprScalar.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64MCTargetDesc.cpp | 143 if (Info->get(Inst.getOpcode()).OpInfo[LblOperand].OperandType
|
| /external/llvm/lib/Target/R600/MCTargetDesc/ |
| SIMCCodeEmitter.cpp | 77 unsigned RegClass = Desc.OpInfo[OpNo].RegClass;
|
| /external/llvm/lib/Target/ARM/ |
| Thumb2SizeReduction.cpp | 730 if (i < NumOps && MCID.OpInfo[i].isOptionalDef())
732 if (SkipPred && MCID.OpInfo[i].isPredicate())
766 if (MCID.OpInfo[i].isPredicate())
776 !MCID.OpInfo[i].isPredicate()) {
826 if (i < NumOps && MCID.OpInfo[i].isOptionalDef())
836 bool isPred = (i < NumOps && MCID.OpInfo[i].isPredicate());
[all...] |
| ARMCodeEmitter.cpp | [all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| CodeGenPrepare.cpp | [all...] |
| /external/llvm/lib/CodeGen/ |
| TargetInstrInfo.cpp | 45 short RegClass = MCID.OpInfo[OpNum].RegClass;
46 if (MCID.OpInfo[OpNum].isLookupPtrRegClass())
225 if (MCID.OpInfo[i].isPredicate()) {
|
| TargetSchedule.cpp | 213 && !DefMI->getDesc().OpInfo[DefOperIdx].isOptionalDef()) {
|
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMMCTargetDesc.cpp | 252 if (Info->get(Inst.getOpcode()).OpInfo[0].OperandType!=MCOI::OPERAND_PCREL)
|
| /external/llvm/lib/Target/R600/ |
| SIISelLowering.cpp | 696 int OpClassID = Desc.OpInfo[Op.getResNo()].RegClass;
815 unsigned RegClass = Desc->OpInfo[Op].RegClass;
852 unsigned RegClass = Desc->OpInfo[Op].RegClass;
864 unsigned OtherRegClass = Desc->OpInfo[NumDefs].RegClass;
886 unsigned OtherRegClass = DescE64->OpInfo[Op].RegClass;
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| R600InstrInfo.cpp | 253 switch (MI->getDesc().OpInfo->RegClass) {
|
| /external/llvm/lib/Target/Mips/AsmParser/ |
| MipsAsmParser.cpp | 464 const MCOperandInfo &OpInfo = MCID.OpInfo[i];
465 if ((OpInfo.OperandType == MCOI::OPERAND_MEMORY)
466 || (OpInfo.OperandType == MCOI::OPERAND_UNKNOWN)) {
[all...] |
