| /external/llvm/lib/Target/ARM/ |
| Thumb2RegisterInfo.h | 37 unsigned PredReg = 0,
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| Thumb1RegisterInfo.h | 43 unsigned PredReg = 0,
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| Thumb2InstrInfo.h | 70 ARMCC::CondCodes getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
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| Thumb2RegisterInfo.cpp | 39 ARMCC::CondCodes Pred, unsigned PredReg,
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| ARMLoadStoreOptimizer.cpp | 95 ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch,
109 unsigned PredReg,
115 ARMCC::CondCodes Pred, unsigned PredReg,
286 unsigned PredReg, unsigned Scratch, DebugLoc dl,
340 .addImm(Pred).addReg(PredReg).addReg(0);
351 .addImm(Pred).addReg(PredReg);
371 ARMCC::CondCodes Pred, unsigned PredReg,
416 Pred, PredReg, Scratch, dl, Regs, ImpDefs))
448 ARMCC::CondCodes Pred, unsigned PredReg,
499 Base, false, Opcode, Pred, PredReg, Scratch, dl, Merges)
[all...] |
| Thumb2InstrInfo.cpp | 61 unsigned PredReg = 0;
62 ARMCC::CondCodes CC = getInstrPredicate(Tail, PredReg);
109 unsigned PredReg = 0;
110 return getITInstrPredicate(MBBI, PredReg) == ARMCC::AL;
215 ARMCC::CondCodes Pred, unsigned PredReg,
230 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
237 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
246 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
252 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
438 unsigned PredReg;
[all...] |
| ARMBaseInstrInfo.h | 366 ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
387 ARMCC::CondCodes Pred, unsigned PredReg,
393 ARMCC::CondCodes Pred, unsigned PredReg,
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| ARMBaseRegisterInfo.h | 167 unsigned PredReg = 0,
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| Thumb2ITBlockPass.cpp | 169 unsigned PredReg = 0;
170 ARMCC::CondCodes CC = getITInstrPredicate(MI, PredReg);
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| ARMBaseRegisterInfo.cpp | 390 unsigned PredReg, unsigned MIFlags) const {
401 .addImm(0).addImm(Pred).addReg(PredReg)
744 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
752 Offset, Pred, PredReg, TII);
756 Offset, Pred, PredReg, TII);
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| MLxExpansionPass.cpp | 284 unsigned PredReg = MI->getOperand(++NextOp).getReg();
297 MIB.addImm(Pred).addReg(PredReg);
309 MIB.addImm(Pred).addReg(PredReg);
|
| Thumb2SizeReduction.cpp | 583 unsigned PredReg = 0;
584 if (getInstrPredicate(MI, PredReg) == ARMCC::AL) {
687 unsigned PredReg = 0;
688 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
784 unsigned PredReg = 0;
785 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
[all...] |
| Thumb1RegisterInfo.cpp | 69 ARMCC::CondCodes Pred, unsigned PredReg,
80 .addConstantPoolIndex(Idx).addImm(Pred).addReg(PredReg)
373 unsigned PredReg;
374 if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) {
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| ARMFrameLowering.cpp | 123 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
126 Pred, PredReg, TII, MIFlags);
129 Pred, PredReg, TII, MIFlags);
[all...] |
| ARMExpandPseudoInsts.cpp | 615 unsigned PredReg = 0;
616 ARMCC::CondCodes Pred = getInstrPredicate(&MI, PredReg);
[all...] |
| ARMConstantIslandPass.cpp | [all...] |
| ARMBaseInstrInfo.cpp | [all...] |
| ARMISelDAGToDAG.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonHardwareLoops.cpp | 500 unsigned PredReg = Cond[Cond.size()-1].getReg();
501 MachineInstr *CondI = MRI->getVRegDef(PredReg);
[all...] |
