| /art/runtime/ |
| gc_map.h | 86 size_t RegWidth() const {
103 return NativeOffsetWidth() + RegWidth();
|
| thread.cc | [all...] |
| /art/runtime/verifier/ |
| dex_gc_map.h | 73 size_t RegWidth() const {
104 return DexPcWidth() + RegWidth();
|
| method_verifier.cc | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelDAGToDAG.cpp | 66 template<unsigned RegWidth>
68 return SelectCVTFixedPosOperand(N, FixedPos, RegWidth);
84 unsigned RegWidth);
92 template<unsigned RegWidth>
94 return SelectTSTBOperand(N, FixedPos, RegWidth);
97 bool SelectTSTBOperand(SDValue N, SDValue &FixedPos, unsigned RegWidth);
117 unsigned RegWidth) {
141 if (FBits == 0 || FBits > RegWidth) return false;
179 uint32_t RegWidth = N.getValueType().getSizeInBits();
184 if (!A64Imms::isLogicalImm(RegWidth, CN->getZExtValue(), Bits)
[all...] |
| /external/llvm/lib/Target/AArch64/Utils/ |
| AArch64BaseInfo.cpp | 946 bool A64Imms::isLogicalImm(unsigned RegWidth, uint64_t Imm, uint32_t &Bits) {
955 for (RepeatWidth = RegWidth; RepeatWidth > 1; RepeatWidth /= 2) {
964 for (unsigned i = RepeatWidth; i < RegWidth; i += RepeatWidth) {
979 Rotation = RegWidth == 64 ? CountLeadingOnes_64(Imm)
1021 bool A64Imms::isLogicalImmBits(unsigned RegWidth, uint32_t Bits,
1029 if (RegWidth == 32 && N != 0) return false;
1062 for (unsigned i = 1; i < RegWidth / Width; ++i) {
1070 bool A64Imms::isMOVZImm(int RegWidth, uint64_t Value, int &UImm16, int &Shift) {
1072 if (RegWidth == 32 && (Value & ~0xffffffffULL))
1075 for (int i = 0; i < RegWidth; i += 16)
[all...] |
| AArch64BaseInfo.h | [all...] |
| /external/llvm/lib/Target/AArch64/AsmParser/ |
| AArch64AsmParser.cpp | 330 template<unsigned RegWidth> bool isBitfieldWidth() const {
336 return CE->getValue() >= 1 && CE->getValue() <= RegWidth;
339 template<int RegWidth>
346 return CE->getValue() >= 1 && CE->getValue() <= RegWidth;
402 template<unsigned RegWidth> bool isLogicalImm() const {
409 return A64Imms::isLogicalImm(RegWidth, CE->getValue(), Bits);
412 template<unsigned RegWidth> bool isLogicalImmMOV() const {
413 if (!isLogicalImm<RegWidth>()) return false;
420 return !A64Imms::isMOVZImm(RegWidth, CE->getValue(), UImm16, Shift)
421 && !A64Imms::isMOVNImm(RegWidth, CE->getValue(), UImm16, Shift)
[all...] |
| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| AArch64InstPrinter.cpp | 122 template<unsigned RegWidth> void
126 unsigned LSB = ImmROp.getImm() == 0 ? 0 : RegWidth - ImmROp.getImm();
231 template<unsigned RegWidth> void
236 A64Imms::isLogicalImmBits(RegWidth, MO.getImm(), Val);
|
| AArch64InstPrinter.h | 57 template<unsigned RegWidth>
89 template<unsigned RegWidth>
|
| /external/llvm/lib/Target/AArch64/Disassembler/ |
| AArch64Disassembler.cpp | 116 template<int RegWidth>
122 template<int RegWidth>
418 template<int RegWidth>
426 if (RegWidth == 32 && Shift > 1) return MCDisassembler::Fail;
433 template<int RegWidth>
439 if (!A64Imms::isLogicalImmBits(RegWidth, Bits, Imm))
|
| /external/llvm/include/llvm/Target/ |
| TargetLowering.h | 643 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
644 return (BitWidth + RegWidth - 1) / RegWidth;
[all...] |
| /art/oatdump/ |
| oatdump.cc | 452 size_t num_regs = map.RegWidth() * 8;
530 size_t num_regs = map.RegWidth() * 8;
[all...] |
| /art/compiler/dex/quick/ |
| codegen_util.cc | 645 dex_gc_map.RegWidth());
[all...] |
